Design And Implementation Of Low Power SRAM On 28 Nanometer Technology

Compute In-Memory(CIM)is an effective way to solve the performance and power bottleneck of traditional von Neumann computer architecture.However,as Compute In-Memory reduces delay and power consumption caused by traditional von Neumann architecture data transmission,the demand for power consumption of memory such as Static Random Access Memory(SRAM)is increasing.The most straightforward way to reduce SRAM power consumption is to reduce the SRAM supply voltage.Although the reduction of the power supply voltage can reduce the power consumption of the SRAM by a square factor,it will also cause a certain loss of the read and write performance of the SRAM.Adding an assist circuit structure to the peripheral circuit is a method for effectively improving the read and write performance of the SRAM.However,traditional assist circuit can lose another performance while improving read or write performance.Therefore,it is important to combine multiple assist circuit technologies and realize low-power SRAM design.This paper focuses on the following two aspects of low-power SRAM design.On the one hand,this paper combines and optimizes the ground voltage boost,bit line voltage reduction and bit line charge recovery technology,and redesigns the SRAM cell and the column selector of the read/write separation structure based on these technologies.In the method,when the SRAM writes data,the leakage charge recovery from the half-selection cell’s bit-line is used to drive the ground voltage rise of the allselection cell,and the SRAM all-select cell’s write margin is increased;meanwhile,the bit-line voltage of the half-selection cell is lowered due to the leakage charge,which improves the read static noise margin of the half-selected cell.On the other hand,this paper combines the word line voltage overdrive and word line voltage underdrive technology to propose a new two-step control word line voltage assist circuit.This technology reduces the word line voltage to the underdrive voltage when the SRAM reads data,and improves the read static noise margin of the SRAM.When the SRAM writes data,the word line voltage is first raised to the overdrive voltage and then reduced to the underdrive voltage,which increases the write margin of the SRAM and reduce the loss of the SRAM half-selection cell’s read static noise margin caused by the word line voltage overdrive.The low-power SRAM memory cell designed in this paper is subjected to 1000 Monte Carlo simulation experiments.The experimental results show that compared with the traditional structure,the write margin of this design is improved by nearly 33%,and the read static noise margin is improved by nearly 6%.The minimum operating voltage is reduced from 0.65 V to 0.5V.The layout design of the low-power SRAM of this design is carried out and verified by post-simulation.The experimental results show that compared with the traditional structure,the write time of this design is reduced by10% at 0.65 V.And at 0.5V,the Static and dynamic power consumption of this design are reduced by more than 40% and 30%,compared with the traditional structure whose operation voltage is 0.65V.