Design Of Write-enhanced 12-transistor SRAM Cell Based On TFAT Device

Thanks to the development of integrated circuit manufacturing technology,the size of devices is shrinking and the integration of chips is getting higher and higher,which greatly accelerates the miniaturization of electronic terminal products such as mobile phones and computers.However,with the continuous improvement of integration,the power consumption of the chip is also increasing.Static Random-Access Memory(SRAM),as the core component of the system chip,occupies the main area of the chip and becomes the main source of power consumption.Usually,the most direct way to reduce the power consumption is to reduce the supply voltage,but with the decrease of the supply voltage,the performance index of the traditional Metal-Oxide-Semiconductor Field Effect Transistor(MOSFET)will be greatly reduced,and the sub-threshold swing of the MOSFET can not exceed 60mv/dec because of Ludwig Boltzmann’s thermodynamics.The Tunnel Field-Effect Transistor(TFET)has a strong competitive advantage in low power consumption applications because its conduction mechanism is band-band tunneling,which effectively breaks the limit of traditional MOSFET sub-threshold swing.However,the asymmetry of source and drain of TFETS leads to its oneway conductivity,which challenges the design of low-power circuits based on TFETS.In this paper,a new 12-tube SRAM cell topology is proposed based on the analysis of TFET and the requirement of SRAM circuit Low-power electronics.The work of this paper is as follows:1.The structure and working mechanism of MOSFET and TFET are compared and analyzed.Because of the asymmetry of source and drain of TFET,it is analyzed in detail when TFET is used as transmission tube,including the problems faced by the topology of traditional SRAM 6 cell in the case of source inside connection and source outside connection,and analyze the advantages and disadvantages of TFET-type SRAM cell.2.On the basis of the above analysis,a new 12-tube TFET SRAM cell structure is proposed,and the working principle of the cell is introduced in detail,based on this cell,the common semi-selection problems in the design of storage array are analyzed.3.The performance analysis and simulation of the proposed 12-transistor TFET-SRAM cell structure are completed.In terms of power consumption,the proposed 12-transistor TFETSRAM cell circuit can eliminate the positive bias P-I-N current by using TFET-devices stacked in series,compared with 7 tubes TFET SRAM cell,the static power consumption of the circuit is greatly reduced by 128 times.At 0.8 V operating voltage,and the write ability of the circuit is greatly improved by adding two pull-up write auxiliary tubes.In circuit performance,the reading speed of cell is slightly slower than that of 7 tubes TFET-SRAM,but it is affected by positive bias P-I-N current,the reading speed of the whole array structure is affected by the size of the array,even the reading failure will occur.The reading speed of the proposed cell structure is good in the array design.At the same time,the writing speed is similar to that of the existing7-cell TFET SRAM unit,but 68.1% higher than that of the existing 10-cell TFET SRAM unit.On the aspect of cell reliability,the proposed 12-tube TFET SRAM cell has a Static Hold Noise Margin(HSNM)which is 93% higher than the existing 7-tube TFET SRAM cell at 0.8 V operating voltage The Write Noise Margin(WSNM)is 44.7% higher than that of 7 tubes TFET SRAM cell and 81% higher than that of 10 tubes TFET SRAM cell.Therefore,the proposed12-tube TFET SRAM cell has a good competitive advantage in low power application,which provides a reference for the design of TFET ultra-low power SRAM storage system.