Fault Tolerant Algorithm For VLSI Arrays Based On The Switch Structure

In recent years,with the rapid progress of very large-scale integrated circuit(VLSI)integration technology,the scale of integrated circuits has increased,which has greatly improved the performance of integrated chips.Due to their regular structure and convenient implementation methods,VLSI arrays have been widely used in important fields such as microcomputers,radars,and control.However,as the integrated circuit becomes more complicated,the probability of problems in the integrated system is increased,and the stability of the system cannot be effectively guaranteed.Therefore,under the premise of ensuring that VLSI meets the requirements of high performance and high speed,to improve the computing power and reliability of the multi-processor array,fault-tolerant technologies must be used to reconstruct the grid topology.At present,the fault-tolerant technologies used in VLSI arrays mainly include the redundancy method and reduced-order method.The faulttolerant technology based on the reduced-order method mainly studies the reconstruction of two-dimensional and three-dimensional VLSI arrays.Based on the two-dimensional processor array,the problem of reducing the running time when reconstructing the target array is studied.According to the existing reconstruction algorithm,an improved strategy is proposed,based on the shortest path first principle,which effectively reduces the number of access nodes and improves the reconstruction efficiency of the VLSI array.By comparing and analyzing the time complexity of the existing algorithm,the efficiency of the proposed algorithm is proved.The final experimental results prove that the proposed method effectively reduces the running time of reconstruction and improves the efficiency of array reconstruction.Based on the three-dimensional processor array,the problem of increasing the size of the reconstructed target array is studied.Based on obtaining the largest target array,an optimization algorithm for removing the bottleneck surface is proposed.The algorithm uses the logic plane with the most fault processing units to compensate the adjacent logic plane,and the new logical array is obtained after the array is reconstructed.Examples have proved that the algorithm can improve the utilization of processing units and expand the scale of logic arrays.