| With the continuous development of technology,the demand for billion-gate FPGA is increasing in key areas,so this subject designed a billion-gate FPGA based on 28 nm CMOS technology.There are hundreds of millions of transistors transistors which make the phase difference,delay and jitter of the clock more significant.In addition,in order to cope with more and more complex application scenarios,multiple IP cores are embedded in billion-gate FPGA to achieve various functons,and the different clock frequencies between the IP cores put forward higher requirements for the drive clock module.Traditional clock delay adjustment methods,such as clock tree and buffer,have been difficult to deal with such a complex situation,unable to provide high-quality clock to meet the needs,so a dedicated module needs to be designed for clock management.In this paper,we design an configuable phase locked loop embedded in FPGA as a clock management to provide low jitter and wide frequency clock signals for billion-gate FPGA.This paper first introduces the development history of FPGA and PLL,and then analyzes the working principle,circuit characteristics and design requirements of PLL.The s domain model of PLL is built,and the loop characteristics and noise characteristics of charge pump PLL are analyzed.On the basis of theoretical analysis,this paper designs the PLL module as the clock management unit in FPGA,including dynamic reconfiguration circuit,frequency discriminator,charge pump,loop filter,voltage controlled oscillator and frequency divider and pre-start circuit.The innovation of the PLL designed in this paper is mainly reflected in the following three aspects: firstly,configurable design is adopted in several modules,such as frequency discriminator,charge pump,loop filter,lock detection circuit,frequency divider,etc.,which can flexibly adjust the locking speed and locking conditions of the PLL and each attribute of the output signal according to the need,so as to meet the clock requirements of multiple IP cores embedded in billion-gate FPGA.Secondly,in order to better adapt to the complex and changeable application of billion-gate FPGA,the PLL in this paper also designed a dynamic reconfiguration circuit based on SRAM cell array,which modified the storage information of specified SRAM cell through read/write signals and address signals,and realized the reconfiguration of PLL without affecting the work of other FPGA modules,it greatly improves the flexibility of PLL.Finally,in order to meet the need of billion-gate FPGA for faster locking speed of PLL,a pre-start mechanism is added to make the VCOS oscillate in advance by using the configuration time of the PLL to the entry time of the reference signal,which speeds up the locking speed of the PLL;The PLL embedded in FPGA is designed in 28 nm CMOS process.This paper completed the following work: circuit design,layout design,simulation test and board level test.The test results show that the PLL designed in this paper can work normally.The input clock frequency range of the PLL is 19MHz-800 MHz,and the output clock frequency range is 6.25MHz-800 MHz.The frequency division ratio,duty cycle and phase shift of the output clock can be configured correctly.The lock time of PLL is far less than 100μs,and the maximum output clock jitter is 455 ps @ 6.25 MHz.PLL can realize dynamic reconfiguration correctly,and the performance of each sub-module meets the requirements.The receiving frequency range of frequency discriminator is 19MHz-450 MHz,and the oscillation frequency of VCO is 800MHz-1600 MHz. |
