Novel fast locking digital phase locked loop: Behavioral modeling and simulations using VHDL-AMS

A novel successive approximation fast locking digital phase lock loop (SAR DPLL) is presented and behaviorally modeled using VHDL-AMS. The DPLL operation includes two stages: (1) a novel course tuning stage which employs a successive approximation algorithm which is similar to the algorithm employed in SAR analog-to-digital converters (ADCs) and (2) a fine tuning stage which is similar to conventional DPLLs. The coarse tuning stage includes a frequency comparator, a successive approximation register, a digital-to-analog converter (DAC) and control logic.;A novel flash digital phase lock loop is also behaviorally modeled and presented. The coarse tuning stage includes a frequency comparator array, encoder and digital-to-analog converter. Lock time comparison between successive approximation, flash and conventional DPLL is performed to demonstrate the fast locking. The entire design is performed using Ansoft Simplorer.