| With the rapid development of Internet new economy such as network payment and cloud storage,network information leakage incidents occur frequently,posing a high challenge to guarantee the security of network information.RSA algorithm,as a classical asymmetric cryptographic algorithm,is widely used to ensure the security of network information because of its high security.Such as Alipay,We Chat payment and other commonly used payment software internal integration of RSA encryption technology.The surge of user transaction volume at the same time puts forward performance requirements for RSA encryption technology in terms of speed and throughput.Although the large bitwidth key length ensures the security of encryption,it seriously affects the performance of RSA encryption and decryption,and hinders the further development of highperformance RSA cryptographic system.FPGA has many advantages such as high parallelism,low-cost and rich logical resources,which makes it an optimal hardware platform to implement high-performance RSA cryptographic system.In order to realize the high performance of RSA cryptosystem,the following research work is done in this paper.1.In view of the time-consuming problem of the core operation of RSA algorithm,this paper puts forward a kind of parallel asymmetric short integer Montgomery modular multiplication algorithm from the algorithmic level.It uses short integers cross to perform modular multiplication and modular reduction operations,which can shorten the critical path,support multi-module multiplication parallel execution.It can alleviate the impact of long key on the encryption and decryption speed of RSA accelerator,and improve the speed and throughput rate of RSA accelerator.2.Aiming at the problem that too many iterations of the core operation of RSA algorithm affect the speed,this paper proposes a low delay multiplicative parallel circuit structure from the hardware circuit level.Under the premise of not affecting the critical path,the number of iterations of modular multiplication operation can be shortened,so as to realize the design of high-performance RSA accelerator.3.In this paper,a high-performance RSA accelerator is implemented,which can perform RSA encryption and decryption for up to 48 sets of data at the same time.The advantages of the RSA accelerator are verified by comparing it with other similar RSA accelerators from two aspects of core computation-modulus multiplication and RSA computation. |
