Study And Design On High-speed And Low-power ADCs Based On SAR

High-speed and low-power ADCs are getting more and more attention with the advent of 5G and the continuous development of mobile devices.The overall structure of the SAR ADC is simple,containing only a small amount of analog circuits,and has very obvious digital characteristics.Compared with other ADCs,it can better adapt to the advanced process and the low-power applications.However,due to the limitations of the traditional structure and conversion algorithm,SAR ADC is usually used in the applications with low to medium resolution and low to medium speed.Therefore,it has been a hotspot in this field that how to make full use of the high erergy-efficiency of SAR ADC and break its speed limitation in the traditional structure.In this thesis,high-speed and low-power ADCs based on SAR is studied.Firstly,the SAR ADC based on the traditional structure and conversion algorithm is analyzed from the system level,and the factors limiting its speed are explored,and various speed improvement strategies are studied.Then,aiming at the design targets of the system that the resolution is 8 bits,the sampling speed is 1GS/s and the total power consumption is50m W,the 2b/cycle SAR ADC is adopted.At the same time,the split capacitor arrays,the asynchronous SAR logic and other technologies are used to further improve the speed and reduce the power consumption.At last,the circuit design,implementation and the simulation of the ADC are completed.The speed of SAR ADC can be improved by using the 2b/cycle quantization structure,but it will increase the power consumption.To solve this problem,this thesis proposes a novel low-power capacitor switching scheme for 2b/cycle quantization structure.In this scheme,the split capacitor DACs are used.It eliminates the redundant switching operation of the bit capacitor switches,and realizes the direct control of the comparator output to the bit capacitor switches,which reduces the dynamic power consumption of the capacitor DAC and further improves the conversion speed of the system.Compared with the traditional scheme,the average dynamic power consumption of the proposed one is about 31.84%less theoretically.When compared with other 2b/cycle capacitor switching schemes,the speed,accuracy and area can also get improved in the proposed one.Aiming at the quantization characteristics of 2b/cycle,combined with the proposed scheme,the asynchronous SAR logic is adopted in this thesis,which further improves the conversion speed of SAR ADC.This thesis is based on SMIC 55nm CMOS process for circuit design,and the use of Cadence Spectre to complete the simulation.The simulation results show that under the conditions of different temperatures,different process corners and different input signal frequencies,the ENOB of the bootstrapped sampling switch can reach more than 9.96bits;the dynamic comparator driven by a 5GHz synchronous clock takes about 63.1ps to distinguish the input difference of 1m V;the ADC’s INL_max is 1.401LSB,INL_rms is0.898LSB,DNL_max is 1.488LSB,DNL_rms is 0.639LSB;under the condition that the system sampling speed is 1GS/s,when the input signal frequency is 49.8046875MHz,245.1171875 MHz and 489.2578125 MHz,respectively,the ENOB of the ADC can reach more than 7.1 bits;the power consumption including the bootstrapped sampling switches,the comparators,the capacitor DACs and the bit capacitor switches is about 5.7m W.All simulation results above meet the expected targets.The layout of some critical circuits is designed based on SMIC 55nm 2P6M CMOS technology at last.