Design Of 12-bit 5MS/s Low-power SAR Analog-to-digital Converter

Among ADCs of various structures,SAR ADCs have more advantages in power consumption and area due to their successive approximation logic,and the advantages become more obvious with the development of CMOS technology.The improvement of SAR ADC speed and accuracy usually comes at the expense of power consumption.Low power consumption in the same working state has become an important direction of SAR ADC research.This paper designs a 12-bit 5MS/s low-power successive approximation analog-to-digital converter.First,compared to the traditional binary weighted DAC and the Vcm-based capacitor DAC,the bridge capacitor DAC structure has poor linearity,but its coupling capacitance reduces the total capacitance value and the energy required for voltage switching.Secondly,the capacitor voltage switch uses a transmission gate structure to switch between high and low levels.In order to reduce noise and improve accuracy of sampling switch and Vcm switch,a gate voltage bootstrap circuit whose control signal has nothing to do with the input is adopted,and multiple switches share a gate voltage bootstrap circuit to reduce area and power consumption.Multi-channel function expansion adopts the principle of gate voltage bootstrap,nine signal paths share a gate voltage bootstrap circuit,and complete opening and closing of each signal channel is realized through a boost circuit.Then design a dynamic comparator based on the open-loop comparator combined with the dynamic concept.The accuracy is improved by copying the first-stage integrator,and the second-stage latch uses an asynchronous circuit to latch the comparison result of the comparator according to the output of the integrator.A high-quality output signal is achieved through a shaping circuit.Finally,a D flip-flop is used to design the control logic.The first layer is controlled by a clock to realize the shift function,and the second layer collects and transmits the comparison result of the comparator according to the shift result.The designed low-power SAR ADC is realized by 0.11 um CMOS process,and the power supply voltage is 1.65～5V.The designed SAR ADC is tested for different power supply voltage,process angle,input signal frequency and temperature.The simulation results show that under normal conditions,THD is-82.99 dB,SNDR is 73.19 dB,ENOB is 11.86,and power consumption is 0.488 mW at low voltage,the power consumption is5.675 mW under high voltage.