Design Of A Successive Approximation Analog-to-digital Converter Applied In DSP

Modern electronic systems store and process signals in the digital domain.In order for the system to be interconnected with analog signals in the real world,it is necessary to convert between analog and digital signals.Therefore,analog-to-digital converters(ADCs)have become an essential part of modern electronic systems.In order to adapt to the development of large-scale integrated circuits,how to achieve low-power,high-speed,high-precision analog-to-digital converters(ADCs)has always been a hot and difficult point in today’s research.This thesis firstly analyzes the SAR ADC applied to the DSP chip to obtain the design indicators,followed by the principle analysis and design considerations of the key modules,and selects the most suitable structure for design.Finally,the circuit simulation and layout realization are carried out.First,for the design of the DAC part,using a switching algorithm based on common-mode voltage reset,only 11-bit DAC can meet the requirements of a 12-bit SAR ADC,so a segmented capacitor array with high seven bits and low four bits is used.Compared with the traditional switching algorithm,the capacitor area is reduced and the power consumption is reduced.Second,for the design of low-power and low-noise comparators,the structure of dynamic pre-amplification and latching is used to improve the speed of the comparator while reducing noise,and use the output offset calibration technology to reduce the offset to ensure accuracy.Third,in order to improve the sampling speed,this paper adopts the asynchronous timing sequence,which avoids the use of high-speed external clocks required in the synchronous timing sequence and improves the clock utilization rate.The circuit is designed based on the UMC 55nm process,and the pre/post simulation of the circuit and the realization of the layout are completed under the Cadence platform,and finally the chip test is completed.The area occupied by the ADC is 513×277 um~2.The test results after tape-out show that under the 3 V power supply voltage,the sampling speed is 1.25 MS/s,and the input signal frequency is 9.765625KHz,the signal-to-noise distortion ratio(SNDR)is 66.04 d B,The spurious dynamic range(SFDR)is 80.8 d B,the total harmonic distortion(THD)is-74.4 d B,the power consumption is 15 m W,and the ADC performance is excellent,which meets the design requirements.