Design And Implementation Of FLASH And STT-MRAM Storage System Based On FPGA

With the development of society,the amount of data generated by humans is increasing,and the challenges of storage systems in terms of capacity and performance are also increasing.Traditional storage systems use DRAM to cache data.Due to the volatile nature of DRAM,data is lost after power failure,making the traditional storage system unable to meet current social needs.The new memory STT-MRAM is a non-volatile memory,and has the advantages of reading and writing speed comparabled to DRAM and unlimited erasing and writing resistance,making it one of the candidates to replace DRAM.Therefore,the STT-MRAM,which replaces DRAM,has been adopted to design and bulid a new storge system in this work.It was coordinated data reading and writing by combination between the software and hardware.The main contents are listed,as follows:(1)The selection of storage system components and PCB hardware circuit design were introduced in detail,and the design of hardware circuits are emphasized.The hardware design mainly includes FPGA systems part,memory part and power supply part.In addition,the Or CAD Capture CIS was used for completing the hardware schematic design,and PCB Editor for the layout of PCB components.(2)In this work,the serial communication between the host and the FPGA chip was realized using Lab VIEW software.The data is sent serially to the FPGA hardware system through the Lab VIEW program,and the serial port program function is verified by the simulated serial port software Configure Virtual Serial Port Driver,which basically realizes the integrity of the communication between the host and the FPGA.(3)Some modules,such as UART communication module,FLASH controller module and STT-MRAM controller module,etc.were designed by the FPGA chip based on VIVADO software,which are used to receive data and control the data reading and writing between each memory.Moreover,the simulation results on VIVADO software demonstrates that the control of FLASH and STT-MRAM memory has been realized.The controller uses the ECC check algorithm to check the read and write data to enhance the reliability of the data.At the same time,taking into account the data instability caused by the Open Block of FLASH particles,adding another page of data after the edge page was adopted to improve the the data reliability.The FLASH and STT-MRAM storage system based on FPGA was designed.The data is sent by the host and first written into the STT-MRAM memory.Once the memory is ’full’,the read enable signal is activated,leading to the data read out,and then written successfully into the FLASH memory.The feasibility of the system has been verified through simulation.