Research And FPGA Implementation Of Layered Partial Parallel LDPC Codec

Low density parity check code is a linear block code with excellent error correction performance.It is very suitable for parallel computing and hardware implementation.Today's wireless communication technology has reached a gigabit rate,which requires the use of a gigabit rate LDPC codec.The gigabit rate LDPC codec is implemented using a fully parallel structure,resulting in a very high resource occupancy rate of the codec.In view of the above problems,this thesis designs an LDPC codec with high throughput and moderate resource occupation.At the same time,the code rate can be configured through parameters.The main work is as follows:1.From the two aspects of the complexity of hardware implementation and the resource occupation of the encoder,various encoding algorithms of LDPC codes are analyzed.Based on the structural characteristics of QC-LDPC codes,an encoding algorithm based on QC-LDPC codes is proposed.Finally,the design structure of a configurable LDPC encoder is proposed,and an LDPC encoder with 4 configurable code rates is realized,and the function of the encoder is verified.The FPGA chip based on XILINX Artix-7 synthesizes the encoder,and the result shows that the maximum clock frequency supported is 144.42 MHz,and the maximum throughput rate of the system can reach 2.205 Gbps to 3.584 Gbps.2.The four LDPC decoding algorithms are analyzed in terms of their performance,complexity and hardware implementation,and performance simulations of the four algorithms are given.This thesis proposes a layered double normalized Min-Sum algorithm,which performs different normalization operations on the minimum and the second smallest value.Compared with the LNMS algorithm,the amount of calculation is the same,but the decoding performance is improved by 0.05 d B.Finally,the fixed-point quantization scheme of the decoder is explored.3.According to the characteristics of the layered decoding algorithm,a layered half-parallel decoding architecture with a single permutation network is proposed,and a pipeline of the layered semi-parallel decoding is designed.In order to reduce the consumption of hardware resources,a half-parallel decoding architecture is adopted.The permutation network structure in the decoder is optimized,and a single permutation network is used to complete the cyclic shift operation.Finally,a high-throughput LDPC decoder with 4 code rates is designed,and the function of the decoder is verified.The FPGA chip based on XILINX Artix-7 synthesizes the decoder.The comprehensive results show that the hardware implementation scheme takes up moderate resources,and decoder supports a maximum clock frequency of 167.12 MHz.The system's maximum throughput rate can reach 2.339 Gbps to 6.239 Gbps.