Research And Implementation Of Layered-Full-Parallel Decoder Of QC-LDPC Codes

Low-Density Parity-Check(LDPC)Code is a kind of channel coding with the features of very close to Shannon limit(channel capacity).It is widely applied in modern communication system since it has powerful error-correcting ability.Because of excellent performance and high throughput.LDPC Code has been accepted as the channel coding standard of 5G mobile communications system.In this thesis,based on theory analysis and hardware simulations,QC-LDPC Codes suggested by the CCSDS have been studied and implemented.In addition,an entire software simulation system including encoding,modulation,noise adding,demodulation,quantilation and decoding is established.Taking both complexity and throughput into consideration,the improved Layered Min-Sum Decoding Algorithm(LMSD)Algorithm is applied in this scheme.A LDPC decoder with an improved structure and low complexity,named Layered Full-Parallel(LFP)decoder,is designed.This improved decoder solves some problems of resource consuming and utilization in traditional Partial-Parallel structure,and achieves higher hardware utilization.The improved LFP decoder mainly consists of I/O Buffer,Message Processing Unit(MPU)Modules,Data Memory Modules and Controller,etc.In allocation of hardware resource,a posteriori probability(APP)message and channel initialization information are stored in the same Memory Modules,which decreases half of the memory.Meanwhile,message passing in vertical achieved by MPU,which saves hardware costs of Variable Node Module.The key module MPU is designed with pipeline structuration,which lowers the latency of critical path and improves the frequency of decoder.Also,the operation of relative offset is used between different layers for layered full-parallel update and throughput improvement.Moreover,LMSD Algorithm accelerates the iterative decoding and achieves larger throughput.The hardware simulations and tests shows that,the throughput capacity of the proposed decoder is up to 473.2Mbps with the working frequency of 302.7MHz and 10 iterations.Furthermore,the requirement of hardware implementation is less than 1/4 of the traditional Partial-Parallel QC-LDPC decoders.