Design And Verification Of DDR4 Controller

Since the appearance of the von Neumann architecture,the processor and memory have been regarded as the core of the computer system.The system puts the running program data into the memory and reads it from it when needed.Therefore,the data transfer rate between the processor and the memory directly determines the performance of the system.The hardware specification of the memory is certainly an important factor affecting the transmission rate,however,the role of the memory controller in the transmission cannot be ignored.As a bridge between the processor and the memory,the memory controller not only determines the memory type,memory frequency,maximum memory capacity and other important parameters that the system can use,but also controls the entire data transmission process.This thesis proposes a DDR4 controller design scheme for the data storage and transmission requirements of the system-on-chip,combined with the functional characteristics and pin information of the DDR4 memory.First of all,deep research on various bus architectures of So C,select high-performance,high-flexibility AXI bus for designing the interface between the system and the controller to transmit data and control information.Secondly,based on the comparison and analysis of multiple interface protocols,the memory controller selects the APB bus to design the configuration interface and uses the DFI interface to connect to the external DDR PHY.Thirdly,according to the internal function division of the controller,the controller is divided into interface module,arbitration module,memory access scheduling module,timing control module,refresh module,configuration module,command decoding module and DFI transmission module and design them one by one.In-depth analysis of the impact of the newly added Bank Group structure on the read and write timing of DDR4 memory,while taking into account the characteristics of precharging,activation and other operations during continuous read and write of memory,a design based on "page hit" and different BG memory access commands is designed,and the scheduling mechanism of the priority principle is applied to the memory access scheduling module.Finally,use the Verilog hardware description language to complete the design of the memory controller.Build a verification testbench,write test stimulus and perform simulation verification,analyze the verification results to make the controller meet the design requirements.In order to simulate real application scenarios,the verification platform uses the DDR4 virtual model provided by Micron and the standardized DDR PHY to build a complete transmission link.The overall verification work uses VCS software for simulation testing,and locates problems in verification and design by analyzing the generated log and waveform files.Modify the design code and test stimulus,repeat the simulation test,and finally increase the comprehensive coverage rate of the overall verification to more than98%,indicating that the verification work has basically covered all test points and reached a high level of completeness.The memory controller successfully implemented the DDR4 memory initialization test,read and write transmission,refresh control,configuration parameters and other operations,and passed the DDR4 memory access test with a maximum frequency of 3200 MHz.The results show that the designed controller meets the expected functional requirements and achieves the design goals.