Design And UVM Verification Of Configurable DDR4 Controller

As transistor sizes have shrunk,the performance of both processors and memory has increased.The reason for the huge performance gap between today’s processors and memory is that memory performance doubles every 10 years.Therefore,the processor must wait for multiple clock cycles to receive data from memory,which is known as a memory wall.As a bridge between bus and memory,the performance of memory controller is one of the important factors affecting memory bandwidth.DDR4 is the abbreviation of Double-Data-Rate fourth generation synchronous dynamic random access memory,and it is also one of the most widely used memories.Therefore,the research on DDR4 memory controller is of certain value.This thesis performs design and verification work on the memory controller.DDR4 memory has a new bank group feature compared with traditional memory.In view of this feature,this thesis improves and designs a new polling scheduling method on the traditional memory access scheduling architecture to complete the scheduling of different bank groups and applies it to the memory access scheduling module.Compared with the traditional memory access scheduling strategy,the designed memory access scheduling strategy makes the command interval of each memory access operation of the same type change from a minimum of 5 memory clock cycles to 4 memory clock cycles,which increases the memory access efficiency to a certain extent.Second,the high-performance bus AXI is selected as the command and data interface of the memory controller,and the high-speed bus AHB is selected as the register configuration interface.Finally,a top-down design approach is used to study each sub-module in the memory controller in detail and to develop a specific design framework and methodology.The whole memory controller is divided into AXI processing module,memory access scheduling module,main control module,data control module,refresh control module,DFI interface module and register module.The design of DDR4 memory controller is completed by using Verilog HDL hardware description language.Based on the design of memory controller,a verification platform based on general verification methodology is built.Firstly,after in-depth study of the working mechanism and component composition of the general verification methodology,eight verification function points are extracted according to the functional characteristics of the memory controller.Secondly,the verification platform is built,and 10 test cases are created to verify the function of the memory controller.Finally,the verification results are analyzed in combination with the simulation waveform and code coverage,so that the final code coverage reaches 100% to ensure the completeness of the verification.The design and verification results show that the designed DDR4 memory controller satisfies all the design requirements and is able to perform access memory operations correctly,and the required timing parameters can be configured according to the requirements to achieve support for three rates of SDRAM: slow 1600 Mbps,medium 2400 Mbps and high 3200 Mbps.The designed scheduling policy is functionally correct and can schedule the access commands as expected.The memory controller can control DDR4 memory for initialization,refresh and other common operations.