Design And Implementation Of A General Built-in Self-test Circuit For DDR SDRAM

At present,integrated circuits are developing very rapidly,with larger scales and higher levels of integration.As an extremely important category of chips,the scale of memory chips has also become larger and more complex.DDR SDRAM is the most common type of memory chips.Due to the increase in the scale of DDR and the increase in integration,the difficulty of DDR testing has increased exponentially.Therefore,how to improve the test quality and test efficiency of DDR and reduce the test cost have become a key research issue.The traditional test method of DDR is to write test vectors manually and the test efficiency of this method is very low.It is no longer suitable for the testing of DDR with high-complexity.However,the modern commonly used way to test DDR through CPU running software is not only low in test efficiency,but also high in test cost.In order to solve the problems of test quality,test efficiency and test cost of DDR,this paper focuses on the common faults of DDR SDRAM in the manufacturing process,such as fixed faults,bridging faults,transmission faults,coupling faults and address faults,etc.,and Three test algorithms,such as march c,interconnect,and checkerboard,are designed and improved for these failures.Then,based on the principle,timing and performance of DDR SDRAM,a general built-in self-test circuit for DDR SDRAM that contains three test algorithms is designed.Compared with the modern commonly used way to test DDR through CPU running software,the use of BIST to test DDR has greatly improved the test quality and test efficiency,and the test cost has also been significantly reduced,which significantly shortens the time to market for DDR.After introducing the three test algorithms and the principle,timing and performance of DDR SDRAM,this paper uses structural block diagrams,state transition diagrams,etc.,to introduce the design ideas of BIST circuit and uses Verilog HDL language to describe the circuit.After the circuit design is completed,use the UVM random verification platform to verify the design,and then perform FPGA board-level verification,logic synthesis,static timing analysis and consistency check on the design.The results show that the design meets the expected requirements,and the overall coverage rate of common faults in the manufacturing process of DDR SDRAM is above 98%,and at the same time,the test efficiency is improved and the test cost is reduced.Compared with the traditional test circuits,the area of the BIST circuit has only increased by about 1%.