A CPPLL Design Based On Relaxation Oscillato

In the field of PLL,charge pump phase-locked loop can realize the phase synchronization of output signal and input clock signal to achieve the purpose of stable frequency.Compared with traditional PLL,it has such advantages as fast locking,low power consumption,low jitter,etc.Because of the merits of charge pump PLL,it has a wide range of applications in frequency doubling and synthesis,offset reduction and jitter reduction,etc.With the continuous development of the level of integrated circuit,the chip becomes more integrated and its feature size keep shrinking,which asks for a higher requirement for the performance of charge pump PLL.Therefore,the study of high performance charge pump PLL is of great significance and has become a research hotspot at home and abroad.The subject originates from an enterprise project.A CMOS third-order charge pump phaselocked loop is designed to provide clean,jitter free and stable periodic pulse signal.Based on the in-depth study of the structure and working principle of the charge pump PLL,the stability of the system is analyzed and the loop parameters are designed in this paper.What’s more,MATLAB is used to simulate the amplitude-frequency and phase-frequency characteristics of the phase-locked loop system and complete behavioral-level modeling and simulation.The simulation results show that the system can be stable within a certain period of time,verifying the stability and feasibility of the system design.Based on the design of charge pump PLL system parameters,phase and frequency detector,charge pump and voltage controlled oscillator module circuit are designed in this paper.In terms of the design of phase and frequency detector,the dead-zone effect of the frequency discriminator is analyzed.The method of adding delay module to the circuit increases the width of the reset pulse and effectively eliminates the dead zone.For the charge pump design,bootstrap structure is used to suppress the charge sharing effect caused by the parasitic capacitance of transistor.The channel length modulation effect is suppressed by the common source and common gate current mirror structure,and the current mismatch is reduced.In this way,when the output voltage is in the range of 0.2V to 1.6V,the current mismatch is less than 5p A.What’s more,CMOS transmission gate is used as charge and discharge switch to solve the problems of charge injection and charge feedthrough.Since the VCO is the main source of noise,in order to prevent the signal even order harmonic and the phase noise in the circuit,the relaxation voltage-controlled oscillator circuit structure is adopted,and the V-I differential circuit is used to converts the control voltage to current.Post simulation of phase noise shows that the oscillator achieves lower phase noise,and the noise at 1MHz is less than-120 d Bc/Hz.Based on TSMC 0.13μm CMOS process,the overall circuit simulation,layout and post simulation of the charge pump phase-locked loop are completed in this paper.The simulation results reveal that when the input reference frequency is in the range of 600 k Hz-2.48 MHz and the supply voltage is 1.8V,the PLL can realize the locking of both frequency and phase.When the reference frequency is in the range of 2MHz,it has a locking time of 80μs and a period jitter of no more than 5ns,with a low overall power consumption of only 0.55 m W.By this,the design of the PLL circuit of the charge pump can meet the design criteria and output clean,jitter-free and stable periodic pulse signals.