Research On Charge Pump Phase-Locked Loop For Ethernet Chip

Ethernet technology is widely used in the information industry and has become an indispensable part of modern communication systems.A high-performance charge pump phase-locked loop(CPPLL)circuit is the key technology to ensure the accurate data transmission of Ethernet communication chips in high-speed environment.Based on the design of 10/100/1000 Mbps Ethernet communication chip,this paper designs a low phase noise charge pump phase-locked loop circuit for its high-speed communication environment.The specific work of this paper is as follows:Firstly,the stability of the charge pump phase locked loop is analyzed,and the loop parameter values are derived.Using the Simulink tool on the MATLAB platform,the mathematical model of the third order charge pump phase locked loop is constructed,and the calculated parameter values are substituted to design the phase locked loop circuit system.The simulation results show that the charge pump phase locked loop has a bandwidth of1.25 MHz and a phase margin of 70。,indicates that the calculated parameter value is reasonable.Secondly,based on RS latch structure,a frequency phase detector with large range,high sensitivity and short dead time is designed.To solve the non ideal factors of charge pump module,a low mismatch and high performance charge pump is designed.The charge pump circuit uses a transmission gate structure to replace a single MOS switch to reduce the impact of channel charge injection effect,and adds a Dummy branch to suppress the charge sharing effect.Compared with the traditional charge pump,it compensates the influence of non-ideal effect on the circuit and helps to improve the stability of the phase-locked loop.A low phase noise four stage differential ring voltage controlled oscillator based on a Maneatis symmetric load differential delay unit is designed.A buffer shaping circuit is added to the output of the delay unit to convert the output waveform into a square wave signal with a duty ratio of 50%,achieving full swing output of COMS,while improving the drive capability of the circuit.In order to adapt to high frequency conversion in a phase locked loop,a frequency divider with a frequency division ratio of 16/20 is designed using high-speed D flip-flops and digital logic gates.Among them,the frequency division ratio of the circuit is controlled by a digital selector,which meets the frequency requirements of the Ethernet chip under different operating modes.In addition,in order to reduce the noise impact of the power supply signal on the phase locked loop,a low voltage differential linear regulator with fast transient response is also designed to provide stable operating voltage for each sub module of the circuit.This circuit introduces a transient detection circuit composed of a capacitance coupled current mirror,which is not only convenient to detect the output voltage jump,but also increases the charging and discharging capacity of the power transistor,and is also conducive to reducing the power consumption of the phase-locked loop circuit.A bandgap circuit that eliminates zero degeneracy points is designed to provide a bias voltage for the low dropout regulator,the voltage controlled oscillator and charge pump.Finally,on the basis of the above modules,based on the SMIC 0.13μm standard COMS library,the power supply voltage is 2.5V.The simulation is performed using Spectre software.The results show that when the loop is locked,the range of phase detector is-1.94π～1.94π,and the reset pulse time is 195 ps,which can effectively eliminate the jitter caused by the dead time.The charge pump charge and discharge current difference is less than 300 n A,and the matching degree is good.The phase noise of the VCO is-92.46 d Bc/Hz when the frequency offset is1 MHz,which has good anti-noise performance.When the output voltage of the loop filter is stable at 824 m Vthe,circuit locking time is 6.8μs,and the total jitter is less than 16 ps.The charge pump phase-locked loop circuit meets the clock signal requirements of Ethernet chip and reaches the design index.