Research And Design Of High Efficiency Parallel Dual Channel Buck DC-DC

With the rapid development of science and technology,power management chip is widely used in communication,computer,aerospace and other industries.Based on the basic principle of non isolated buck DC-DC,combined with the research of key technologies,in response to the development trend of high efficiency and high load current,a high efficiency parallel dual channel buck DC-DC converter with peak current mode is designed.In this thesis,the pulse skipping mode and burst mode are designed to solve the problem of low efficiency of continuous conduction mode under low load current.The chip can be selected from the continuous conduction mode,pulse skipping mode and burst mode through the MODE pin.The pulse skipping mode realizes the function of skipping certain working cycles by shielding the pulse signal through RS trigger,which reduces the switching times under low load current and reduces the switching loss to improve the conversion efficiency.In the burst mode,the chip switches between the standby state and the DCM state with fixed peak inductor current through the state selection comparator.The inductor current in the DCM state is much higher than that in the pulse skipping mode,which has less switching times and higher conversion efficiency.A frequency adaptive piecewise linear slope compensation circuit is designed to solve the problem of subharmonic oscillation in high duty cycle operation under peak current mode,which ensures the stability of the current loop at all switching frequencies.The active clamping technology is designed to solve the problem of slope compensation reducing the load capacity.The peak hold circuit is used to generate a dynamic voltage proportional to the peak slope compensation current to clamp the output of the error amplifier,so that the load capacity of the system is independent of the duty cycle,and the working state of the burst mode is optimized.The dynamic voltage participates in the burst mode control loop so that the threshold load current of burst mode and the peak current of inductor in DCM state remain unchanged at any duty cycle.The dual channel parallel function is designed to achieve the design goal of high load current.When the second channel VFB pin is connected to the input voltage,the chip will enter the parallel mode by pin multiplexing technology.The master-slave current sharing control method is used to realize the dual channel current sharing.The 180° phase difference is set between the working cycles of the channels to reduce the ripple of input voltage and output voltage.A simplified small signal model is established to analyze the stability of the voltage loop,and the parameters of the off chip frequency compensation network are set.The chip uses 0.35 μm BCD process,based on Cadence platform,using Spectre simulator for simulation.The results show that the starting waveform of the chip is fast and smooth in three modes,and the working state is stable after starting;the performance of load step response and input step response is good,the output voltage overshoot and downshoot are small,and the recovery time is fast;when the two channels are used in parallel,the starting is normal,the two channels interleave normally,and the output voltage ripple is significantly reduced compared with the single channel;the peak load capacity can reach 10 A,the peak conversion efficiency can reach 95%,meeting the design goals of high efficiency and hige load current.