Design And Implementation Of MCU Reusable Verification Platform Based On RISC-?

With the development of integrated circuits faster and faster,the complexity of MCU(Micro Control Unit)has increased dramatically,making it more and more difficult to verify the MCU.Reusable verification refers to the reuse of the developer's existing verification environment.On the basis of shortening the verification workload,it has improved the completeness of MCU verification.Therefore,research on reusable MCU system verification platform has important reference value and practical significance for the current functional verification field.The verification object of this article has been a certain MCU chip based on the RISC-?(Reduced Instruction Set Computing V)processor core.At the same time,the RISC-? MCU processor core system and the high-speed bus outside the core has been as specific research targets to building the verification platform.By analyzing function points,applying randomized incentives,collecting function coverage and reporting self-checking,the thesis has implemented a relatively complete implementation of the RISC-? processor core functions and the MCU off-core bus and IP(Interlectual Proerty)interaction module Functional verification.Based on the coverage-driven approach,this article has analyzed the incentive requirements in the RISC-? processor core and constructed a specific instruction template.The instruction generator has been used to design a constrained random instruction generation platform.Then,based on the general verification methodology,the core module has been verified by allowing the excitation signal to traverse all the instruction classes supported by the processor,and a highly flexible and configurable random instruction generation platform has been realized.In addition,in order to verify whether the function of the system's off-core bus is correct,a general verification methodology has been adopted,and a general verification development platform based on the AXI4(Advanced Extensible Interface)bus protocol has been designed for the off-core bus system.The platform uses randomized general transaction processing as a verification incentive,and has been able to monitor the key information of the data output.Finally,the built AXI4 bus verification platform has been used to interact with the IP-level modules,and it's functions have been fully verified,and the verification platform has been reused.Throughout the verification process,the platform monitoring module have been used to monitor the key signals and compared with the reference model.At the same time,the simulation tool have been used to collect and analyze the coverage of the design code.The verification of the bus system has been completed in a relatively short time.The research results of the verification of the reusable MCU in this paper have shown that all data transmission and reception of the AXI4 bus verification platform have been correct,a total of 2868 sets of data have been automatically compared successfully,the running simulation time is 11.32 s,and the code coverage rate reaches 100%.The refactored I2C(Inter-Integrated Circuit)and DDR3(Double Data Rate)verification environments have also been able to work normally,and the test results of their basic functions have shown that they are correct and reliable.In addition,the RISC-? instruction generation platform designed by constraining random instruction set functions has been able to run independently and automatically.And the code coverage of each module has been above 96%,and the function coverage has reached 100%.The verification goals required in this thesis have been achieved.