Design Of 6～18GHz CMOS Low Noise Amplifier

In recent years,with the development of phased array radar and the progress of phased array technology,the application field of the 6～18GHz band has been paid more and more attention.The T/R module in the radar system adopts monolithic integration,which can not only meet the needs of military applications,but also has low power consumption,small size and low cost.As the first stage of receiving link,low noise amplifier（LNA）firstly amplifies weak signal with low noise.Its performance directly determines the performance of receiving link.Therefore,a 6～18GHz low noise amplifier with certain gain and good noise performance is very important for T/R module.In this thesis,a 40nm CMOS process was used to design an LNA with a bandwidth of6～18GHz.The core circuit adopts the cascade structure of current multiplexing,and the output matching circuit adopts the cascade structure.The resistance feedback structure is used to match the wideband input impedance,and the noise figure reaches the minimum noise figure at high frequency.The gate peak inductor and drain load inductor are used to improve gain at high frequency.The circuit design,pre-simulation,layout design and electromagnetic simulation are shown.The results show that the power gain range of the low noise amplifier is 14.2～15.1d B,and the noise figure is 3.9～5.2d B at 27℃and TT process corner.The S₁₁ is less than-11.7d B,and the S₂₂ is less than-11.8d B.The input compression point of 1d B is larger than-17.4d Bm.The operating voltage of the LNA is 1.2V.The total current of the circuit is 23.8m A.All the performance of the low noise amplifier in this thesis meets the requirements,and the LNA can be used in phased array radar system.