Domestic Design Of FPGA Chip For Digital Controller Of Accelerator Power Supply

In recent years,affected by a series of events such as the Sino-US trade war and the shortage of cores during the epidemic,many domestic companies and scientific research institutions that rely on US chips are facing the risk of chip supply at any time.The power digital control system,which occupies a very important position in The China Spallation Neutron Source system of the large scientific device,currently uses the FPGA Cyclone series of Altera Corporation in the United States.In order to avoid the influence of chip supply or cost soaring on the power supply control system of The China Spallation Neutron Source,a set of DC power digital control system with domestic FPGA chip as the core is developed in this thesis.In this thesis,the FMQL45T900 FPGA chip of Fudan Microelectronics is selected as the main control chip of the domestic power supply digital controller.The chip has4-core CPU and 350 K programmable logic resources,which can meet the needs of the current accelerator power control system.According to the characteristics of chip hardware resources and power control requirements,this thesis completes the design of the hardware backplane of the power digital controller and the peripheral circuit of the core board,and passes the port function on-board test.The core of the controller program designed in this thesis is composed of three parts: control program,fault protection program and communication program.The main problems solved by the control program are:(1)For disturbances from two different sources,such as power grid fluctuations and load temperature changes,this thesis adopts a double closed-loop PID control algorithm with the current loop as the outer loop and the voltage loop as the inner loop.(2)In order to improve the control accuracy of the controller and solve the problem that FPGA cannot directly handle floating-point number operations,this thesis develops 10 single-and double-precision floating-point number operation modules that conform to the IEEE754 standard protocol,and optimizes the timing design to reduce module clock consumption.The pipeline operation function is provided,which greatly improves the operation efficiency of the module.(3)In order to improve the resolution of PWM when the main frequency and PWM period are certain,this thesis adopts the digital average method.(4)Aiming at the problem that real-time continuous acquisition cannot be performed due to the fact that the change frequency of the internal register value of the controller is much faster than the serial communication rate,a data acquisition system is developed in this thesis to realize the continuous acquisition and analysis of the specified register value at any time period.The main problem of the fault protection program is to identify and protect the 12 common faults of the accelerator power supply.The communication program mainly solves the data interaction between the digital controller and the touch screen and the host computer.This part of the program is implemented on the ARM of the domestic chip,and uses the Free RTOS real-time operating system to schedule the tasks of the touch screen communication and the host computer communication.Finally,the long-term operation stability and safety test is completed on the accelerator DC power supply.The test results show that the domestic FPGA power supply digital controller designed in this thesis can achieve continuous 9 hours,the current stability is better than 70ppm(0.007%)output,and the repeatability Better than 100 ppm,meeting DC power control requirements.