Research And Design Of Encryption And Decryption Coprocessor Based On RSA/SHA-256

With the breakthrough of 5G technology,the continuous expansion of modern Internet of Things and cloud computing technology,people are paying more and more attention to the security of personal privacy data in the era of exponential growth of information.At present,the network has penetrated into every field of our life.It is ubiquitous in production,shopping,travel,home and other life scenes.Due to the openness and freedom of the network itself,the possibility of personal information being stolen or tampered with is greatly increased.Therefore,in this era of the Internet of everything,how to better protect the security of personal privacy data is becoming more and more important.In this thesis,based on the basic cryptography theory,by summarizing the current domestic and foreign development status and industry research results,aiming at the current Internet of Things,cloud computing,data center for data security and chip power consumption requirements,a encryption and decryption coprocessor based on RSA and SHA-256 algorithm is designed.The coprocessor supports 32-bit embedded operating system,encryption and decryption operation based on RSA algorithm,data digest operation based on SHA-256 algorithm,and can complete data encryption and decryption,message authentication and digital signature with the cooperation of software.Meanwhile,it is compatible with AXI4.0 system bus protocol.It can be widely used in the application environment where a large number of data need to be stored and transmitted safely.The major contents can be summarized as follows:Firstly,at the software level,based on the traditional SHA-256 algorithm,a high throughput per unit area is proposed,which is convenient for hardware design and implementation.Sha-256 algorithm is based on the combination of multiple compression functions.Based on the current RSA algorithm,a 4096bit wide RSA algorithm with higher security is implemented.On the basis of the traditional mode-power algorithm,exponential mask and random operation are added to improve the anti-power attack ability of RSA algorithm.For the module multiplication algorithm part,a high speed Montgomery domain module multiplication algorithm based on multiple pipeline structure with higher data throughput is proposed.The improved SHA-256 and RSA algorithms are modeled and simulated by Python programming language.The correctness and feasibility of the improved SHA-256 and RSA algorithms are verified by comparison with the running results of the standard algorithm.Secondly,In the aspect of hardware circuit design,the SHA-256 hardware operation module is designed and implemented based on four different structures of single-round compression function,two-round compression function combination,four-round compression function combination and 65-round depth pipeline.Through data performance comparison,the proposed structure of multi-round compression function combination has higher data throughput per unit area.In RSA module,the modular power operation structure is designed and implemented to resist power consumption attack.Based on the core modulo multiplication operation of modulo power realization structure,a high performance Montgomery domain modulo multiplier with base 32 bits and double pipeline structure is proposed,which improves the performance of Montgomery domain modulo multiplier with slightly increased area and power consumption.For the design of encryption and decryption coprocessor,the peripheral data interface,internal control and computing core are designed respectively.The final encryption and decryption coprocessor has the advantages of high security,low area,high running speed and so on.With the support of TSMC’s next-generation 7nm process conditions,the circuit synthesis was performed using Synopsys DC synthesis tool.The final synthesis frequency was1.5GHz,the synthesis area was 22853μm~2,and the power consumption was 32.84 mw.The comprehensive area and operating power consumption are reduced compared with the design index.Finally,Based on the design of traditional UVM validation methodology,a portable automated random validation platform was built to complete regression validation and coverage collection.The function correctness and completeness of the design are verified by code coverage and function coverage.The prototype verification platform is built by Xilinx ZYNQ series chip,and the actual feasibility of the designed encryption and decryption coprocessor is verified.The final design of encryption and decryption coprocessor can meet the requirements of the target environment application,and can be widely used in the SOC system design of Internet of Things security chip.