Algorithm-based Advanced Encryption Standard (aes) Encryption Chip Design

The encryption product has wide application in future, with the development of Information Technology in the recent years. This thesis is focus on the design of AES algorithm security chip.Firstly, the thesis discusses the theory of AES encryption algorithm, which is safe,efficient, convenient and nimble in use.Secondly, the design of AES algorithm ASIC is completed, which includes structure partition and function definition. Each part is depicted with Verilog HDL. By using Verilog-XL tools, behavior simulation is done and the chip logic is realized which encrypts data with 128bit cipher keys. Based on APEX20K chip and Synplify and Quartus2.1 tools, FPGA synthesis and P&R are finished, and the timing simulation is done. The simulation results indicate the correctness of the circuit design.