Research On Implementation Architecture Of High Throughput LDPC Hardware Decoder For QKD Error Correction Protocol

During the communication process of quantum key distribution(QKD),due to the influence of channel noise or eavesdropper(Eve)monitoring,the keys obtained by the legitimate communication parties are inconsistent.In order to obtain the same key,information reconciliation is required to alleviate the key error.In the high-speed QKD system,with the continuous bit rate increase,tenser requirements are put forward for the information reconciliation module.The classic QKD error correction algorithms such as the BBBSS protocol,the Cascade protocol and the Winnow protocol cannot simultaneously guarantee high reconciliation efficiency and high throughput.Low density parity check(LDPC)codes have been introduced into QKD information reconciliation research in recent years due to their very small number of interactions and excellent decoding performance.This paper proposes an LDPC decoder hardware architecture with high reconciliation efficiency and high throughput for existing QKD systems.Specifically,in terms of reconciliation efficiency optimization,this paper presents the code rate adjustable scheme which can be compatible with different channels with various initial bit error rate,and the puncturing algorithm which determines the optimal puncturing position of the target bit rate.This scheme guarantess that the information reconciliation can be adapted to a very wide range of bit error rates.This solution solves the problem that the reconciliation efficiency deteriorates with the change of the initial bit error of the channel when a single code rate is applied,and improves the code yield of the QKD system by generating better reconciliation efficiency.In terms of hardware decoder design,the paper conducts the key parameter simulation influencing the decoding performance most importantly,including the bit quantization number,the normalization coefficient and the maximal iteration number.By utilizing the characteristics of the high-level synthesis tools,a general hardware architecture suitable for QC-LDPC codes is proposed.In particular,in order to solve the memory access conflict of single-cycle data acquisition in the iterative decoding process,multiple independent RAMs are used to store the information which can be updated in parallel.The unroll and pipeline instructions are used to optimize the check node and variable node update functions.In general,the partial-parallel update hardware architecture is realized,and the high-throughput hardware LDPC decoder is constructed with low implementation complexity.Finally,the information reconciliation module proposed in this paper is deployed on the Xilinx ZYNQ Ultrascale+ ZCU102 development board and verified with actual QKD data.The experimental results show that the information reconciliation module can be adapted to the wide bit error rate(BER)range of 1.7%-10.6%,while keeping the reconciliation efficiency very high being in in the range of 1-1.32 with the remaining frame error rate of 10-3,and the decoding throughput can reach a very high level of 17.9Mbps-219.3Mbps.