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Reconfigurable Noise-Shaping SAR ADC For Biomedical Signal Processing

Posted on:2024-04-01Degree:MasterType:Thesis
Country:ChinaCandidate:D LuoFull Text:PDF
GTID:2530307157981239Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
In many emerging healthcare applications,such as multimodal medical implants and neural probes,achieving high resolution and energy efficiency are critical factors.However,the higher the resolution,the more stringent the noise requirements on the comparator,resulting in larger power and area of the capacitive digital to analog converter(CDAC),ultimately making SAR ADC lose its energy efficiency advantage.In recent years,Noise-shaping SAR ADC has become an attractive solution,with the advantages of both SAR ADC with low power consumption and high resolution of Sigma-Delta ADC.Aiming at the problems of high power consumption and week shaping ability of traditional second-order noise-shaping SAR ADC,a third-order noise-shaping SAR ADC with a hybrid error control topology of cascaded integrator feedforward(CIFF)and error feedback(EF)is proposed in this article,and a feedback capacitor is added to the system in series with the CDAC.Thus,the filter capacitor is not directly connected to the CDAC.Therefore,the feedback capacitance can be used to adjust the size of the attenuation factor to ensure that the input signal is not attenuated and the feedback signal is attenuated slightly.This EF-CIFF structure provides stronger noise-shaping capability and robustness of higher-order NTF.Additionally,the residual amplification of the EF and CIFF paths only requires a small gain and low-power dynamic amplifier.The proposed noise-shaping SAR ADC works at 160 KS/s sampling frequency under180 nm CMOS process with a 1.8 V supply,and its power consumes only 11.3 μW,With an oversampling rate of 8,it achieves a high ENOB of 15.6 bits.The ADC can switch between high-precision and low-power modes.In high-precision mode,the noise-shaping module is enabled,and a 10-bit SAR ADC is used for higher accuracy.In low-power mode,the noise-shaping module is disabled,the SAR ADC is reconfigured to an 8-bit architecture,and the sampling frequency is reduced to 20 KHz.In this mode,the power consumption is only 0.48 μW,and the ENOB is 7.5 bits at 27 ℃ and tt process corner,with a figure of merit of 149.9 d B.Moreover,the ENOB exceeds 7 bits at different process corners over a temperature range of-40 to 85 degrees.
Keywords/Search Tags:Noise-shaping, EF-CIFF structure, Successive approximation register, Dynamic amplifier, Series connection capacitors
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