Design Of High Frequency And High Efficiency LLC Current Multiplier Control Chip

With the rapid development of modern technology,facing the power supply requirements of huge server arrays,the power supply architecture is also developing towards high density and high efficiency.Multi-level power architectures are widely used in server power supplies due to their wide voltage input range and high energy transfer efficiency.The first-stage pre-regulator module of the latest factorial power architecture converts the DC high voltage into a stable bus voltage,and the second stage converts the bus voltage to the voltage required by the load section through isolation.The LLC topology can maintain high conversion efficiency at high switching frequency due to its soft switching characteristics,and at the same time,the power transformer has a good isolation effect,so it is suitable for use in the second stage of the factorial power topology.In this thesis,I aim to design a high-frequency and high-efficiency LLC current multiplier control chip for the second stage of a factorial power supply architecture.In this thesis,the working principle of the full-bridge LLC is analyzed in detail,and the steady-state working state of the LLC resonant converter is studied based on the fundamental wave equivalent method.The control chip is defined based on the system application scenario and its special drive circuit,and based on the analog control method.It focuses on solving the difficulties of soft start,current sampling and high-precision oscillator in LLC control.The proposed current sampling circuit can directly extract the topology current information,the soft start circuit performs closed-loop control through the current information,and the PWM circuit additionally samples the system driving circuit information to make the dead time controllable on-chip.In order to solve the shortcomings of fixed operating frequency,uncontrollable soft-start time,and inaccurate overcurrent protection in traditional control methods,the control strategy of the chip is optimized to make the control chip suitable for more application scenarios.The designed control chip is designed and simulated by using 0.25μm BCD process,and the functions of the on-chip oscillator module,high-speed comparator module,current sampling module and each protection module are individually verified.Simulation verification,to meet the individual design indicators of each module.At the same time,the overall simulation is carried out in combination with the off-chip system parameters,and the core functions such as the steady-state working state of the system,the soft-start state,the adaptive dead-zone adjustment,the lock-up protection and the hiccup protection are verified.The verification results show that the control chip can fully realize the functions required by the system and meet the expected design indicators.