Research And Design Of Key Technologies For Power Management Chips For Portable Devices

With the continuous development of semiconductor technology,portable devices have developed rapidly in the consumer electronics and wireless electronics markets.For portable electronic devices powered by batteries,power management chips must be able to adjust their output voltage based on widely varying input power supply voltages,and still maintain efficient voltage regulation at low voltage conversion ratios.High integration,high efficiency,high step-down ratio,high power density,low power consumption,and fast transient response requirements are proposed for power management chips.Common power management chips include switched inductor DCDC converters,switched capacitor DC-DC converters,and low dropout regulators(LDOs),each with its own advantages and disadvantages.In this paper,three different types of power management chips are studied and designed for different needs of portable devices for power management chips.The main contents are as follows:(1)To meet the application requirements of high integration and efficiency,the design of a multiphase reconfigurable switched capacitor DC-DC has been completed.The design uses a reconfigurable switched capacitor cell to achieve two voltage conversion ratios of 1/2 and 2/3,achieving a smoother efficiency curve over a wide input and output voltage range;Using a ring oscillator to output a thirteen phase clock interleaved control switched capacitor cell,a smaller output voltage ripple is obtained through multiphase interleaving techniques;Built-in dual power rails and level shifter circuits are used to reduce parallel losses caused by switching actions,greatly improving power conversion efficiency.The chip adopts a 40 nm CMOS process.The measurement results show that the input voltage range is 1.4-1.98 V,the output voltage range is 0.5-1.16 V,and the maximum load current is 30 m A.When the load current is10 m A,the peak conversion efficiency is 71.86%,and the ripple is 32 m V.(2)To meet the application requirements of high step-down ratio and high efficiency,a hybrid tri-path buck DC-DC design has been completed.Compared to the Buck topology,the hybrid three-path buck topology adds two flying capacitors,which means two additional energy transmission paths,one more transmission path than the hybrid dual-path buck converter.The average current on the energy storage inductor is reduced by 50% compared to the Buck topology,thereby reducing the parasitic resistance conduction loss caused by the DCR resistance of the energy storage inductor,and its voltage conversion ratio is lower.Using the state space averaging method to model the topology with small signals,an equivalent mathematical model was obtained,and the overall PWM loop design was ultimately completed.At a TT corner of 25 ℃,the post simulation results show that the input voltage range is 3-4 V,the output voltage range is 0.5-1 V.When the load current is 10 m A,the peak conversion efficiency is81%.After adding a soft start circuit,there is almost no overshoot voltage.(3)Aiming at the application requirements of high integration and low power consumption,the design of an ultra-low power fast transient response CL-LDO has been completed.The main circuit of the LDO adopts a dual mode switching design,which enables the circuit to track and monitor the load current based on the principle of adaptive bias,achieving a quiescent current of only 12 n A at no load;The push-pull structure and dual mode switching are combined to form a co-enhanced transient circuit,which generates a large conversion current for charging and discharging the gate capacitor of the power transistor when the load changes.When the load changes between 200 μA and 20 m A,the recovery time is only 12.3 ns;The stability is analyzed under heavy and light loads,respectively.In addition,auxiliary circuit designs such as ultra low power and high robustness bandgap reference,over temperature,and over current protection have been completed.Under various PVT conditions,the circuit can work normally and stably,achieving good robustness.Finally,all the research work in this paper is summarized,and the shortcomings in the design of the three power management chips in this paper are discussed.Future research directions for improvement are also discussed.