Research And Design About The Transient Response Of High Stability Ldo

Power management unit has increasing role in the present electronic equipments. More and more handled and battery powered applications require the power management unit to extend the battery life and thus the operating life of the electronic devices. Low drop-out (LDO) voltage regulators play a rery important role in the modern power management unit for it can provide a good regulation and a fast transient response while providing clean and ripple-free output voltage. Industry and technology are pushing towards complete system-on-chip(SoC) design solutions including power management. So the recent research focuses on the capacitor-less LDO architecture for SoC solutions.However, the implementation of a capacitor-less LDO is faced with some difficulties of design, and one of the biggest probles is the transient response. When the large output capacitor has been removed, more overshoot and undershoot are expected at the output when the extreme load transient occurs. The transient response of the capacitor-less LDO regulator is dependent on the slew-rate at the gate of the pass transistor(Mpass).Slew-rate at the gate of Mpass is a large value. Based on the analysis on the design challenges of capacitor-less LDO regulator, the theory of negative feedback system is studied at first, then discusses the LDO stability at two aspects:the small signal response of system loop and the large signal response, and research the methods to improve the LDO stability at two points:the frequency compensation and load transient response. Some literatures raised methods to improve the LDO stability, the frequency compensation and load transient response are used in this paper, and the circuit is implementation at last.The LDO in this paper improve the system stability mainly with the dynamic frequency compensation and load transient response enhancement method.(1)A MOS tube whose VGS changes with the working state of the system is connected in series with a capacitor linked between the power transistor’s and LDO’s output, and which forms the dynamic frequency compensation circuit. Since the MOS tube can be equivalent to a dynamic resistance, a dynamic zero point can be obtained here. And this zere point can offset the system’s second pole, so as to improve the system unit gain bandwidth and phase margin.(2)When the load current jump, the tail current of error amplifier has corresponding change. The transient response improvement circuit acquire the current changes, and an amplifier transform this signal into a current which accelerate the charge and discharge to the gate capacitor of the power transistor, so as to improve the large signal stability of LDO.The LDO voltage regulator was designed and simulated in 0.25μm BCD process. By simulation, and the result verification that the dynamic compensation circuit and transient enhancement circuit have obvious improvement effect. The LDO loop simulation show that the circuit has loop bandwidth of 45MHz, and phase margin of about 50°. And result show that the overshoot and undershoot output voltage is respectly 92mV and 89.4mV at a load step of 10mA/us under the typical process.