Reach And Design Of Double Loop Buck Converter Without Off-chip Current Sampling

In recent years,people increasingly rely on the electronics,and these products cannot work without a well-regulated power supply,so the market of power management is growing.Buck converter is favored due to its relatively simple structure,high power conversion efficiency and high reliability.With the development of electronic industry,the requirements of miniaturization,high speed and reliability have gradually increased.So the buck converter has great space for optimization.First of all,some common buck converter topology is proposed,after comprehensive consideration,this thesis use peak current control mode.Then in order to save the chip area,this thesis propose a new topology based on the traditional peak current control mode,the new topology need inductor current sample circuit no more.Then in order to improve the reliability and able to be applied in super charge,a buck converter which can switch between constant output voltage mode and constant output current mode according to load current is proposed.This topology can ensure the stability of both the constant voltage loop and the constant current loop.This topology also can ensure the two loops share one compensation network to save the chip area.A wire compensation function is proposed,the output voltage will higher than the set value according to the load current,to compensate the voltage drop of the charging cable.Then in order to further decrease the chip area,a load current detection circuit without extra pin is proposed.Finally,in order to improve the speed of the converter,the dynamic compensation of the peak current mode buck converter,an output capacitor detector is proposed to ensure the unit gain bandwidth divide the switching frequency is an optimal value which is the best trade-off between unit gain bandwidth and the loop stability with different output capacitor.The circuits in this thesis is designed based on 0.18 um BCD process,and the sub block and entire system are verified by Cadence.The input range of double loop is5V-30 V,the constant output voltage range is 3V-20 V,the switching frequency is220 k Hz,the highest constant output current is 3A,the wire compensation is 50 m V/A.According to the results of the simulation,the voltage and current loops can work in the steady state and two loops can switch correctly,the worst constant current accuracy is99.3%,the performance of the circuit meet the desired goals.As for the capacitor detector,the output capacitor is between 10 u F-100 u F,the worst output capacitor detector accuracy is 89%,meet the desired goals.