Research And Implementation Of Multi-Channel Storage Technology Of Waveform Recorder

With the rapid development of the electronic information industry,comprehensive test scenarios are becoming increasingly complex,which puts forward higher performance index requirements for traditional electronic measuring instruments.As an electronic test instrument that integrates the functions of oscilloscope and data logger,Waveform Recorder has a variety of acquisition board units,and plays an important role in complex systems such as strong and weak current hybrid equipment and simultaneous observation of multiple physical signals.However,the variable combination of multichannel data sampling rate,channel number and storage depth of Waveform Recorder also increases the complexity of data storage function design and implementation.This thesis aims to combine the waveform recorder hardware platform to propose a system storage scheme based on the MIG IP core AXI bus interface,and specifically design and implement each memory function module,At the same time,optimization and improvement are made for different mode characteristics to improve the test efficiency.the main research content is as follows:1)Design and implement DDR3-based trigger storage mechanism.In order to solve the problem of large-capacity multi-source channel data fusion storage and the characteristics that DDR3 cannot read and write access at the same time,a write address control management solution is designed based on the principle of triggered storage.Using AXI burst mechanism and Outstanding transmission characteristics,the pipeline design is optimized to improve the data writing efficiency,and an improved handling method is proposed for the address boundary problem in the storage process.2)Design and implement direct memory point extraction of large-capacity data.In order to further improve the efficiency of reading and displaying waveform overview,this thesis designs the read address control management based on the AXI bus to provide a more efficient waveform post-processing reading method,which can directly extract points from DDR3 to read data.Through the test and verification platform of Waveform Recorder,the reading time of single waveform profile is about 0.6ms at the main clock frequency of 100 MHz.3)Design and implement a partitioned storage controller.The partition controller is designed based on FPGA to achieve high efficiency of waveform capture and manage the multi-frame waveform trigger data address in the partition storage process.Finally,the maximum 4096 frame partition is achieved,and the fixed dead time of waveform capture is reduced to 20 ns within the partition storage time.4)Design and implement real-time record capture function.The real-time recording mode can support 128 channels of data acquisition at the same time.Through the time division multiplexing method and the AXI bus write-response channel handshake feedback,the DDR3 write-and-read control is designed and implemented.When the sampling time base is set to be large,when the user needs to stop randomly,the AXI burst transmission mechanism may lead to a long waiting time for the end of control.For this reason,a fast stop function is designed to ensure that the end of control is around 530 ns.In order to monitor and record the change trend of low-speed signal for a long time,and capture the details of high-speed phenomenon at the same time,double sampling function is designed and implemented based on AXI bus arbitration mechanism.In addition,the system storage function modules in this thesis are based on parametric design,which has strong flexibility,scalability and portability.