| In the 21st century,with the development of information technology and the popularity of electronic devices,the importance of power management chips as a functional management part of electronic devices is self-evident.Among numerous power chips,switching power supplies are highly favored for their excellent system conversion efficiency and reliability,with BUCK converters being the most widely used.Based on the current trend of miniaturization,digitization,high power density,high conversion efficiency,and low EMI in the design of BUCK converters,this article focuses on the characteristics of energy conversion efficiency and low EMI,in order to design a low EMI and efficient BUCK converter.By introducing and analyzing the modulation mode and control mode of the converter,a peak current mode with inductance current limit and strong noise resistance was selected for the control mode of the BUCK converter designed in this thesis.Analyzed the source of losses in the converter and improved system efficiency through corresponding low-power design.In order to reduce errors caused by chip manufacturing and process,a digital trimming module with pre trimming function was designed to reuse the original pins of the chip to ensure the accuracy of the chip.We have designed an on chip clock oscillator with multiple operating modes,which can generate a clock frequency that can be adjusted within a certain range through an external frequency selection resistor.It can operate in external frequency following mode,frequency reversal mode,and spread spectrum mode according to different application scenarios.The spread spectrum mode achieves the effect of reducing the EMI of the converter through frequency jitter technology.Due to the fact that the BUCK converter contains high and low power rails,a level displacement module is proposed for signal transmission between the high and low power rails.Propose a bootstrap module to provide high voltage for normal operation of the upper tube.And a dead time module is used to accurately control the dead time between the upper and lower power transistors,in order to avoid losses caused by the simultaneous conduction of the upper and lower transistors due to too small dead time or a decrease in converter efficiency caused by too large dead time,thereby ensuring the efficiency of the converter.The above solution uses Cadence Virtuoso software on the Linux platform,using 0.25μm BCD process simulation.The BUCK converter designed in this article has a wide input range from 5.5V to 65 V,a maximum stable load current of 3.5A,and an adjustable operating frequency in the range of 200 KHz to 3MHz based on external frequency selection resistors.In typical applications,the energy conversion efficiency of the converter can reach over 85%.When the input voltage is 12 V and the output voltage is 5V,and the load current is 2A,the energy conversion efficiency can reach a maximum value of 94.6%.By comparing and simulating before and after using frequency jitter technology,the noise energy was reduced by 12 dB.Overall,the converter in this article meets the design goal of low EMI and high energy conversion efficiency. |
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