Implementation Of IEEE1588 Hardware Timestamp Based On GMII Interface

With the rapid development of network technology,Ethernet has been used widely in various fields due to its generality of protocol and flexible network topology.The protocol of IEEE1588 based on Ethernet overcomes the bottleneck of NTP technology,and improves the clock synchronization accuracy to the sub-microsecond level by using the hardware timestamp.Network time synchronization technology is playing an important role in 5G communication,intelligent grid and other fields.Implementing the IEEE 1588 protocol mainly adopts two technical means:One is based on the PHY chip that supports hardware timestamp,and the other is based on FPGA to develop the IP core.The realization of IEEE 1588 protocol based on FPGA has the characteristics of short development cycle,low design cost and high flexibility,so realizing IEEE1588 protocol by using this scheme has important engineering research significance.After analyzing the previous architecture scheme of implementing the IEEE 1588 protocol based on FPGA,the paper designs a system architecture of IEEE 1588 that can support one-step and two-step mode.After the AHB bus interface scheme and the GMII interface scheme are compared in terms of synchronization accuracy and implementation difficulty based on this architecture,this paper implements the IEEE 1588 protocol based on the GMII interface.Design two modules of parsing and processing frame to process IEEE 15 88 event messages;design the real-time clock module to provide hardware timestamp for the system;design the module of managing registers:one is to provide an communication interface between the ARM layer and logic layer,the other is to complete the functions of data transmission and control;design the pulse per second output module to provide PPS(Pulse Per Second)signal for the measurement of synchronization accuracy;realize the transplantation of the IEEE1588 protocol stack at the ARM layer:add related driver functions to complete the data interaction between the ARM layer and the logic layer.Based on the software and hardware system that has been completed,the test environment was built to test the time synchronization accuracy in different modes.The influence of frequency adjustment strategy on time synchronization accuracy is compared and analyzed;the problem of timestamp transmission across clock domains is solved;the influence of clock source accuracy and path delay uncertainty on synchronization accuracy is compared and analyzed.The time synchronization system designed in this paper completes the one-step and two-step functions specified by the IEEE1588 protocol,and supports two path delay measurement mechanisms,E2E and P2P.The synchronization accuracy reaches 11ns(3σ),which meets the requirements of time synchronization in the fields of networked test systems and so on.