Electrical Model Of Junctionless Nanowire Transistor And Study On Interface Trap Effect

The advent of transistors and the rapid development of integrated circuits have greatly promoted the progress of science and technology.With the development of semiconductor industry,the feature size of transistors has now reached the technology node below 5 nm.It is necessary to manufacture devices with smaller and smaller sizes,while maintaining the improvement of electrical characteristics.New device structures and simplified fabrication process need to be developed urgently.To overcome these technical difficulties,silicon-based junctionless nanowire transistor has emerged as the times require.It has no PN junction and no doping concentration gradient from drain to source,which can be regarded as a heavily doped gate-controlled resistor.This structure is conductive to reducing thermal budget in the fabrication process and simplifying the fabrication process of conventional devices.Therefore,it is considered to be an important development direction of nanoscale MOSFET in the future.Fin FET becomes the mainstream structure of MOSFET because of its excellent ability to suppress short channel effects,high integration,and compatibility with traditional CMOS process.In this paper,the operating mechanisms,fabrication process and the influence of interface traps of the Fin-gate silicon-based junctionless nanowire transistor will be studied.The details of the study are as follows:1、Basic structure and working principle of silicon-based junctionless nanowire transistors are introduced.The excellent electrical characteristics of the junctionless transistor are demonstrated by comparing it with inversion and accumulation transistors.Then,based on one-dimensional Poisson’s equation,the main electrical parameters of silicon-based junctionless nanowire transistors are derived and analyzed theoretically which is helpful to understand physical connotation in depth.It provides a theoretical basis to further improve the electrical characteristics of the device through the optimization of fabrication process.2、Analytical model of the double-gate junctionless transistor is constructed,and the approximate solution of Poisson’s equation is given based on the depletion approximation model.The COMSOL Multiphysics simulation software is used to build a two-dimensional model of the double-gate junctionless transistor.We simulate and analyze the effects of different parameters such as channel length,silicon layer thickness,gate oxide thickness,doping concentration and interface trap concentration on the junctionless transistors.The effect of drain-source current and threshold voltage of junctionless transistors,and the simulation results are matched with theoretical calculation results.In addition,the effect of short channel effects on the electrical properties of junctionless transistors is also investigated.At the same time,the simulation results are compared with theoretical calculation results and these two data match well.3、The fabrication process of silicon-based junctionless nanowire transistor is designed and optimized,including ion implantation,preparation of silicon nanowire,gate dielectric layer oxidation,polysilicon gate preparation,opening ohmic contact holes and other process steps.Finally,silicon nanowires with a cross section of about30 nm×30 nm are obtained,which is prepared for the subsequent experimental test.4、The electrical characteristics of the fabricated heavily N-doped devices are tested and studied in the temperature range of 10 K～300 K.Random telegraph signal and current hysteresis are observed at low temperature,i.e.,T=10 K,which is caused by interface traps in the device.At low temperature,interface traps can generate mobility fluctuations in the process of emitting and capturing charges,resulting in obvious random telegraph signal noise.By counting the dependence of the capture/emission time on gate voltage,the depth of the trap in the oxide is found to be0.35 nm away from Si/Si O₂ interface.The interface trap density of 1.9×10¹²cm^-2 can be obtained from the variation trend of the subthreshold swing with temperature.In addition,COMSOL simulation software was used to build a three-dimensional model with the same structure as experimental device,and the experimental results were matched with the simulation results by adding different interface trap densities,and the trap level position was 0.18 e V below the intrinsic Fermi level.Through above work,the key issues of the electrical characteristics model of nanoscale junctionless transistors and the influence of interface traps on the performance of transistors are studied in this paper,which has important guiding significance for nanoscale junctionless transistors.