Design Of Rate Compatible Spatially Coupled LDPC Codes Based On FPGA

Compared with the LDPC code,the code rate compatible SC-LDPC（Space-coupled Low-Density Parity-Check,SC-LDPC）codes can reduce the transmission delay,and has received extensive attention to the academic community,because of its special sliding window decoding method.At present,the main research direction of the rate-compatible SC-LDPC codes is to reduce algorithm complexity and reduce the occupation of decoding resources.In terms of FPGA design,there is relatively little research.In view of the above problems,in order to meet the applicability requirements of flexible conversion to multiple code rates of SC-LDPC codes in digital baseband communication,this paper conducts in-depth research on the matrix construction and encoding and decoding algorithms of rate compatible SC-LDPC codes,and comprehensively considers hardware resource occupation.The FPGA design and implementation of the code rate compatible SC-LDPC codec are carried out in terms of the codec performance and the codec performance.The main contents of the paper are as follows:Firstly,combined with the research background and research status of SC-LDPC codes,the representation method of SC-LDPC codes,the basic principles of SC-LDPC codes and the commonly used rate compatibility methods are studied.On this basis,an improved method is designed.Check matrix construction algorithm.In the aspect of coding algorithm,several common coding algorithms of SC-LDPC codes are studied,and an iterative coding algorithm suitable for hardware implementation is found.In terms of decoding algorithm,several commonly used decoding algorithms are studied.Through comparison and analysis,a decoding algorithm with lower complexity,suitable for hardware implementation and excellent decoding performance is selected,and its optimization and improvement are made.Secondly,using the Verilog hardware programming language,combined with the optimized and improved coding algorithm,the code rate compatible SC-LDPC code encoder is designed,and the code rate compatible with 1/2,1/3 and 2/3 is realized.And simulate and analyze the correctness of the encoder,resource occupancy,IP core implementation and other functions.Combined with the optimized and improved decoding algorithm,a decoder compatible with SC-LDPC code rate is designed,and a decoder compatible with three code rates of 1/2,1/3,and 2/3 is realized,and the simulation analysis is carried out.Functions such as decoder correctness,resource occupancy,and IP core realization are realized.Finally,this paper tests from three aspects:system performance,board-level verification,and hardware interface synthesis.Under three different code rates,the performance indicators of the synthesized codec are tested.The test results show that the codec’s bit error rate performance is lower than 10^-4 orders of magnitude when the signal-to-noise ratio is 4d B under the Gaussian white noise channel to meet the system designed indicators,and complete the system design.