Design Of A High-Precision Hybrid Sigma Delta ADC Modulator

With the rapid development of signal processing technology,digital-to-analog converters(ADCs)have been widely used as a conversion hub between natural analog signals and information-based digital signals.Among them,the Sigma-delta(Σ-Δ)ADC achieves extremely high performance with oversampling and noise shaping technology,and is widely used in high-precision products in audio,biology,and sensors.In this paper,the modulator circuit of Σ-Δ ADC is studied in terms of high precision and low power consumption,and a hybrid Σ-Δ ADC modulator using SAR ADC as quantizer is designed,and the circuit structure of the modulator is designed.Performance optimization improvements have been made.Firstly,according to the analysis of the circuit structure,system parameters and nonideal factors of the Σ-Δ ADC modulator,the system-level modeling of the Σ-Δ modulator circuit is completed.The ideal model of the modulator circuit is built by MATLAB,and based on the condition of 64 times oversampling rate,the third-order 4-bit discrete CIFF full feedforward structure is used to design the modulator circuit,and the ideal model is added to the ideal model.Non-ideal factors in circuit design.The non-ideal factors are added to the overall circuit of the modulator through the Simulink tool,and the research and inductive analysis of the simulation modeling are carried out.And for the nonlinear problem of SAR multi-bit quantization output,the correction compensation model is used to optimize the output precision of the modulator circuit,and the circuit-level design is carried out based on the simulation results.Secondly,for the hierarchical design of the Σ-Δ modulator circuit and the application of the SAR ADC quantizer,the circuit-level design of the modulator is carried out.The integrator module,SAR ADC quantizer module,DAC module and clock module of the modulator are designed and simulated by the Cadence tool,and the performance of the modulator is optimized by using a fully differential structure in the overall circuit structure.Compared with the traditional integrator structure,this paper adopts a hierarchical structure design,and uses the chopper steady state technology in the first-stage integrator to reduce the interference of low-frequency noise.At the same time,a 4-bit SAR ADC is used to replace the traditional quantizer,which effectively reduces the number of comparators in the quantizer.The capacitor array,comparator and SAR control logic of the SAR ADC are analyzed.By optimizing the capacitor array of the SAR quantizer,the number of capacitors is reduced and the power consumption is further reduced.The DAC unit is extracted by the DWA algorithm,which reduces the mismatch between circuits and ensures the performance of the modulator.Finally,after completing the modulator circuit-level design,the layout optimization design is carried out,and the post-simulation of the modulator is carried out.The Σ-Δmodulator adopts the TSMC 0.18 process design simulation circuit under Cadence.Under the 5V power supply voltage,the 20 k Hz bandwidth,the sampling frequency is 2.5 MHz,and the OSR is 64,the SNDR of 104 d B can be achieved,and the resolution is about 17 bits.The power consumption is 5.98 m W.The simulation result after the layout reaches an SNDR of about 102 d B,and the effective number of digits reaches 16.73 bit.The design of this paper can meet the design requirements,and has a high resolution,which can be widely used in the field of audio signals.