Research On Packet Pipeline Processing Engine Technology For Reconfigurable Network Switching

Computer and communication networks have undergone major changes.The design cost of network equipment is huge,fixed-function hardware accelerators have gradually been unable to adapt to the rapid development of network technology,and due to the increasing complexity of modern networks and the increasing flexibility required by emerging services.The higher the level,this coexistence approach brings great complexity in managing network infrastructure,and the evolving network demands bring enormous challenges to the functionality and performance of network devices.The implementation of traditional Open Flow has insufficient programmable performance,and it is difficult to meet the requirements of protocol-independent processing,which will bring great inconvenience to equipment manufacturers and users.This project originated from the needs of national ministries and commissions,and designed a reconfigurable pipeline processing engine in the network switching chip.Facing the requirements of single-bus 40 Gbps line-speed processing,protocol-independent forwarding,and flexible programmability,a packet pipeline processing engine is designed,which is composed of multiple MAU(Match-Action-Unit)units.The matching module in the MAU unit is based on High-performance matching algorithms such as fuzzy matching,exact matching,and prefix matching are implemented,which can meet the matching of various field types,and can effectively support protocol-independent processing,field identification customization,action customization,and 40 Gbps wire-speed processing capabilities.In view of the needs of multiple matching methods and the high cost of traditional TCAM matching,FSBV is selected as the prefix and fuzzy matching algorithm,and the existing matching structure is optimized according to the pipeline structure,which has more flexibility and adaptability;accurate;The matching adopts the HASH matching algorithm,the hash function adopts the CRC check,and the cuckoo hash is used to optimize it for the hash conflict.After optimization,BV and HASH can achieve 1 clock cycle to complete matching.As the line speed of data packets increases,complex modifications to fields become more difficult,resulting in a requirement that the packet operation processor must be powerful enough to handle the expected type of operation.In this thesis,actions are mapped into micro-instructions,and a variety of actions defined in Open Flow and P4 are implemented in a programmable way through micro-instructions.It supports various set definitions for packet actions and implements actions on data packets.For the data packet forwarding action,a dynamic MAC address bridging scheme is adopted,and the learning and searching of the MAC address realizes the flexible forwarding of the data packet.In this thesis,the EDA simulation platform and the FPGA board-level test environment are carried out for the reconfigurable pipeline processing engine.The simulation covers functional points such as field identification,action customization,port forwarding and wire-speed processing tests,and the reconfigurable pipeline processing engine is completed.Functional Verification.Action execution,forwarding and rate testing are performed on the protocol processing engine through XCVU13P and Test Center packet transmitter,and various protocols including Ethernet,VLAN,IPv4/6,and TCP/UDP are generated through Test Center packet transmitter,which is completed by sending data packets.In the loopback test,the test results show that the engine can meet the 40 Gbps line-speed processing and forwarding capabilities,and can support unicast,multicast and broadcast port forwarding,and the frame loss rate is 0%.Finally,the reconfigurable pipeline processing engine is synthesized based on the UMC 28nm CMOS process.The results show that the processing engine designed in this thesis has a critical path delay of 2.71 ns at 0.81 V and-40 ~oC,and the clock frequency meets the So C requirement of 312.5 MHz.After synthesis,the area is1158261.33μm2,which has passed physical verification and consistency check.