High Speed Design And FPGA Implementation Of Polar Code Encoder And Decoder For 5G Standard

Polar code is the first channel coding scheme that has been proven to achieve the symmetric capacity of binary input discrete memoryless channels.It has received extensive attention from academia and industry due to its definite construction method and low coding and decoding complexity.After years of efforts,advanced decoding algorithms and a variety of Polar code concatenation schemes have been proposed,including cyclic redundancy check codes,parity check codes,etc.The bit error rate performance of mid-length Polar codes makes them comparable to advanced LDPC and Turbo codes.In 2016,Polar code was determined by 3GPP as one of the coding schemes for control channels in the eMBB scenario.In this paper,according to the design standard of Polar code for the control channel of 5G eMBB scene,the realization of the Polar code encoding and decoding algorithm is studied.The main work can be summarized as the following points.1.This paper firstly describes the coding process of the Polar code and the decoding algorithm of the commonly used Polar code,and simulates the bit error rate performance of the Polar code under different decoding algorithms.2.The Polar code coding scheme in the 5G eMBB scenario is given,and the key parameters and processes are sorted out,and the matching decoding scheme is designed for the Polar codes of the uplink and downlink control channels respectively.3.Design encoder and decoder suitable for 5G,and propose strategies to reduce latency:This paper designs a low-latency(parallel processing of sequence search and information bit position search)implementation scheme for the calculation of the bit indication set in the coding architecture? Aiming at the problem that the serial frozen bit insertion delay is too long,a strategy is proposed(information bit storage and serial frozen bit insertion are performed at the same time),and a reasonable Polar encoder and bit insertion operation are selected for parallel processing,which further reduces the processing delay? In addition,for the problem of rate matching and channel interleaving occupying a long time for coding in the uplink coding link,the joint design of the two greatly reduces the coding chain delay? In the downlink coding link,in order to reduce the extra processing delay caused by the real-time online calculation of the interleaving position,a module that can directly perform DCRC bit interleaving is designed.After the comprehensive realization of software,the coding link designed in this paper can reach 300 Mhz frequency on a specific FPGA chip,and the information throughput can reach 82.5Mbps.In terms of decoder design,the decoder structure compatible with different code lengths and rates in the standard is mainly designed,and the quantization bit width in the decoding calculation is determined by bit-true simulation.Afterwards,this paper designs corresponding processing modules for different Polar code cascading schemes,and reduces the hardware calculation and control complexity according to software assistance,and its information throughput can reach 11.3Mbps when the frequency is 140 Mhz.4.Put the designed encoder and decoder into the general communication model and test it on the FPGA development board.In order to verify the functional correctness of the implemented encoder and decoder simply and quickly,an interactive simulation platform based on the serial port is designed for the communication between the PC host computer and the FPGA,in which the PC only needs to send instructions and test parameters to the FPGA,and the corresponding FPGA can measure the performance of the corresponding parameters and draw the performance curve through the PC.