Design And Implementation Of High Efficiency Polar Decoder Based On FPGA

Polar Code is a control channel coding scheme in the fifth-generation mobile communication network(5G)enhanced mobile broadband(eMBB)scenario,and is also a key research object of physical layer technology in 5G systems and next-generation mobile communication networks.The successive cancellation(SC)decoding algorithm of Polar Code has unsatisfactory performance when the code length is short,and the decoding delay is relatively large.The hardware resource consumption of the CRC-Aided Successive Cancellation List(CA-SCL)decoding algorithm based on the Cyclic Redundancy Check(CRC)-assisted decoding algorithm will increase significantly with the increase of the code length.Facing the requirements of low delay and low hardware complexity in future communication scenarios,it is necessary to further design and optimize the Polar Code decoder according to the limitations of high delay and high hardware complexity.This paper firstly introduces the coding algorithm,SC decoding algorithm and CA-SCL decoding algorithm principle of Polar Code,and briefly introduces the basic decoder structure of Polar Code.Then,in order to meet the requirements of low delay and low complexity hardware decoder,a high-efficiency Polar Code hardware decoder scheme is proposed,which combines SC decoding and CA-SCL decoding algorithm.Compared with the traditional CA-SCL decoder,the proposed decoder pays less hardware resources and significantly improves the decoding efficiency,it realizes the balance between hardware resource consumption and decoding delay,and ensures the decoding reliability.In order to reduce the decoder delay,the proposed decoder realizes 8-bit parallel decoding by optimizing the sequence of SC decoding algorithm.On this basis,the decoder optimizes the selection of information bits and the calculation of Path Metric(PM)for the CA-SCL decoding structure,increases the decoding parallelism and reduces the decoding delay.Further,in order to flexibly support different code length and code rate configurations,and reduce hardware resource consumption,this paper adopts the method of time division multiplexing to process the core data.Finally,based on the FPGA evaluation kit of Xilinx Virtex UltraScale+,a Polar Code hardware decoder is implemented,which verifies the hardware structure and function of the high-efficiency Polar Code decoder proposed in the paper.The results show that the test results of the high-efficiency Polar Code decoder proposed in this paper are close to the floating-point simulation results of the traditional decoder,and the decoder has the advantages of flexible configuration and superior performance in hardware resource consumption and decoding delay.