Research On Virtex-7 Chip Modeling And Placement And Routing Visualization Based On VTR

With the explosive demand for constantly updating iterations of applications and Moore’s Law approaching its end,the industry needs to find alternatives to traditional CPUs for highperformance computing.As a programmable semiconductor device,FPGA provides higher performance and flexibility than other programmable platforms,making it a great market potential for 5G communication,edge computing,and other fields.The updating of the underlying process technology of FPGA and the proposal of novel architecture have led to a rapid expansion of the scale,integration and device density of FPGA,which in turn has led to a large gap between the chip architecture researched in the academic field and those used in the commercial field,and to the development difficulties in the research process.Therefore,the construction of resource information model and design-assisted visualization modules for commercial chips is of great significance for exploring and researching commercial chip architecture,which can lead the research direction of the academic field toward commercial chip devices.Combined with the actual usage demands,this paper firstly completes the process of constructing the chip resource information model from three aspects: global FPGA information,logic cell blocks and routing resources by examining the underlying structural characteristics of Xilinx’s Virtex-7 series large-scale commercial chip xc7vx330t-2ffg1761 and using the structured modeling description of the academic open source framework VTR8.0.Based on this chip resource information model,this paper modifies the VTR 8.0framework and uses the open source synthesis tool Yosys to complete the implementation process of the selected commercial chip and circuits from the RTL synthesis stage to the placement and routing stage.Secondly,this paper designs and implements a parsing and rendering module suitable for Virtex-7 commercial chip to fulfill the design capability requirements for functionally complex software systems.The parsing and rendering module firstly analyzes the chip resource information model and the intermediate result information generated during the design implementation phase of VTR 8.0 in reverse by means of the corresponding parsing algorithm;and then completes the visualization of the final implemented circuit placement and routing results by using the rendering algorithm of its sub-assisted rendering visualization module.In this paper,15 circuits of different scales designed for Xilinx 7 series FPGA in Symbiflow are selected as test benchmark circuits to test and verify the completed implementation of the chip resource information model and the parsing and rendering module.The experimental results show that the xc7vx330t-2ffg1761 chip resource information model constructed in this paper has the availability and accuracy to enable the test benchmark circuit to complete the entire flow of RTL synthesis to routing in VTR 8.0.In VTR 8.0 and Vivado,the total running average time spent in the placement and routing stage of the test benchmark circuit is 32.11 seconds and 13.00 seconds respectively.The results show that Vivado runs on average 1.47 times faster than VTR 8.0 during the placement and routing stage in single-threaded mode.In addition,the parsing and rendering module correctly presents the placement view and the routing view of all test benchmark circuits implementations,and the overall parsing average running time for all test benchmark circuits in the parsing and rendering module is 1.583 seconds.