Design Of A 4 Gsps/lane MIPI C-PHY Transceiver

With the rapid development of information technology,mobile devices have a wide range of peripherals and interfaces.The mobile industry process interface(MIPI)defines a series of interface standards to meet the stringent operating conditions of mobile devices.C-PHY is a high-speed and rate-efficient PHY with its unique 3-Phase symbol encoding technology for three-wire three level voltage transmission,which provides high throughput on bandwidth-limited channels.C-PHY have been used in MIPIs camera serial interface(CSI)and display serial interface(DSI).In this paper,a 4Gsymbol/s/lane high-speed interface transceiver circuit based on the MIPI C-PHY specification for bandwidth-limited mobile devices CSI and DSI is designed.Since it delivers 2.28 bits per symbol,data rate of this transceiver is 9.12 Gbps.The main contribution of this paper are:(1)Study the content of MIPI C-PHY specification,construction the C-PHY transceiver link model using ADS tool,design of the digital encoding and decoding logic circuit,and building of the transceiver link in AMS simulation environment of Cadence Virtuoso.(2)Design of the C-PHY transmitter circuit,including designing the clock selection and circuit driver to provide two optional clock inputs for the transmitter.Design of the 12-to-3 Serializer,driver control circuit and pre-emphasis control circuit to provide pre-emphasis driver circuit control signals.Design of the output three-wire pre-emphasis driver circuit providing different pre-emphasis strength for different signal transition to improve the output signal high frequency component of the output signal.(3)Design of the C-PHY receiver circuit and proposed a continuous-time linear equalizer based on the differential comparison unit.The differential comparison unit solves the effect of the continuous change of the common mode level of the differential input signal on the continuous-time linear equalizer of the C-PHY receiver,and realizing the common mode suppression and adjustable high frequency compensation.Design of the clock recovery circuit based on edge detection to reduce the complexity of the clock recovery circuit and save power consumption.(4)Implementation of the transmitter and receiver layout,and post-simulation to verify the transceiver link function and performance.The proposed MIPI C-PHY transmitter and receiver is implemented in SMIC 40 nm IP8M standard CMOS process.It uses 1.1 V supply voltage and achieves symbol rate of4 Gsymbol/s/lane.The transmitter driver output jitter is 0.288 UI,the receiver receive differential data jitter is 0.336 UI,and the clock recovery circuit recovery clock jitter is0.384 UI when operating at the highest transmission rate.The area of the transmitter chip is2.004 mm~2 and the area of the receiver chip is 0.96 mm~2.