Design And Verification Of Receiver Interface Based On MIPI CSI-2 Protocol

With the rapid development of integrated circuit design and manufacturing technology,the rapid iteration of electronic products,people’s requirements for the clarity and resolution of video images are increasing,and the amount of data to be transmitted is getting larger and larger,so the data transmission capacity of traditional interfaces can no longer meet the requirements of high-speed transmission.MIPI CSI-2 interface is used by most electronic equipment manufacturers for image data transmission.In this paper,we first study and introduce the MIPI protocol and APB protocol,and then design the receiver interface based on Verilog HDL language and MIPI CSI-2 protocol.The circuit modules mainly include lane management module,low level protocol module,pixel processing module,decompression module,digital video port module,window cutting module,residual frame filtering module,register module,interrupt module and reset module,and the data transmission between each module conforms to the handshake rule.This receiver uses MIPI D-PHY as the physical layer and interacts with the signal of D-PHY in the channel management module with the transmission rate of 80 Mbps to 2.5Gbps,and the register configuration module is designed for configuring D-PHY.The maximum operating frequency of this design is 125 MHz,supporting four data channels and seven image formats,and the supported image formats include YUV422-8bit,RAW8,RAW10,RAW12,RAW14,and USER＿DEFINED,where the USER＿DEFINED format includes two types of compressed data,a lossless compression of RLE type and a MJPEG type with lossy compression.The lossless compression data transfer mode can improve the transfer efficiency by 95% without affecting the image quality,while the lossy compression data transfer mode can improve the efficiency by approximately 154 times with a high image quality.The design supports ECC checksum for packet headers and CRC checksum for payload data at the low level protocol layer.After the digital video port module packages the pixels in a prescribed format,different channels can be selected for output.In addition,this receiver side can be configured with registers to achieve cropping and residual frame filtering operations on the picture data.After the circuit design is completed,a testbeach is built on the UVM verification methodology and test cases are written to fully verify it.Simulation results show that this receiver can support all data types mentioned above and the module functions correctly.After the regression verification,the coverage was collected and the code coverage was 100% after removing some redundant codes and codes that could not be covered.Finally,the logic synthesis of the receiver circuit was performed,and the total circuit area was about 31,442.08μm2 and the circuit power consumption was about 1.156 m W.