Global Bus Design Of Intelligent Power Chip Based On CAN Bus

With the increasing development of smart devices,more electronic devices are equipped with them,and each device must interact with each other during its working process,which makes the interconnection cumbersome and consumes resources.Therefore,the controller area network with flexible data-rate(CAN FD)bus technology with simple interconnection structure,strong real-time performance,low cost and high security emerges as the times require.At present,the bus technology is widely used in automobiles,ships,small aircraft,industrial automation,environmental control and other fields.With the continuous development of CAN FD bus technology,more research fields in China have begun to pay attention to the research and application of CAN FD and its related technologies.As the core of CAN FD bus technology,CAN FD bus controller is being studied and mastered,which has important theoretical and practical significance for the research and development of domestic CAN FD bus related technologies and the realization of its autonomy.In this thesis,based on the CAN FD bus protocol,the research and design of the CAN FD bus controller with the power chip are carried out.First,based on the in-depth study of the CAN FD bus protocol specification,the"top-down"design idea is adopted to design the system structure of the CAN FD bus controller,so that the sending and receiving processes are independent of each other.Secondly,the integration and division of functional modules are carried out based on its system structure.On the basis of optimizing the functional requirements and technical indicators of each module,the hardware description language VHDL is used to describe and code the functions of each module.After that,the author use Vivado software to simulate and analyze the functions of each module and the overall system,and build a simulation environment for the SOC system-level CAN FD bus network to simulate and analyze the functions of the CAN FD bus controller,such as sending and receiving data and error handling.Board-level verification uses a FPGA development board.Finally,the author completes the logic synthesis,formal verification and placement and routing of the code.In this study,the circuit design,simulation verification and layout design of the CAN FD bus controller IP have been completed.The data transmission rates of the bus controller are usually a low-speed 500Kbps and a high-speed 2Mbps two speed modes,and the high-speed mode can reach a maximum data transmission rate of 5Mbps and reliable data transmission.The logic synthesis of CAN FD bus controller is realized by SMIC 180nm process.The results show that the power consumption of CAN FD bus controller IP is lower than 25m W,and all critical timing paths of the controller meet the timing requirements.At the same time,the logical consistency of the netlist generated after synthesis and its source design code is checked by formal verification.The netlist is then placed and routed,and its congestion and clock tree structure are analyzed and optimized.Thus,the final physical layout is obtained,and the area of the layout is 3460557μm~2.The research results lay the foundation for the tape-out of CAN FD bus controller chip.