Design Of The SRAM-FPGA For Anti-SEU System Based On ICAP

SRAM-based FPGA has abundant resources,powerful computing performance,and it is reconfigurable.With these advantages,SRAM-based FPGA is widely used in the aerospace field.However,there are a large number of high-energy particles in the space environment.SRAM-based FPGA is very sensitive to high-energy particles,and are prone to Single Event Upset(SEU),which may cause circuit failures and cause satellites to fail to work normally.In response to this problem,domestic and foreign scholars have done widely research.The anti-single event upset method adopted in this paper is to read back and scrub the configuration data through the ICAP interface inside the FPGA,and use the RM(2,5)code with stronger error correction ability to replace the commonly used FRAME＿ECC error correction code.It supports error detection and error correction for the inversion of 3 bits,which further improves the error correction capability of the system.In addition,the circuit part where the scrubber is located is also reinforced with three-mode redundancy,which reduces the possibility of single event upset of the scrubber.Error judgment is added to the redundant module,which can identify whether a single event upset occurs in the redundant part in time,and avoid the phenomenon that multiple redundant modules may fail due to accumulation of errors.Through the improvement of the above measures,the reliability of the system is improved.At the same time,in the process of layout and wiring,the circuit to be scrubbed and the scrubber circuit are distributed in a distributed layout,which makes it more convenient to determine the frame address of the circuit to be scrubbed.Finally,the designed system is experimented on the Artix-7 chip developed by Xilinx.The system signal is captured and observed by the Chipscope tool to verify the correctness of the system function.The system is injected with faults to simulate single event upset.Three different types of circuits to be tested are designed.One is a combinational logic circuit,the other is a sequential logic circuit,and third circuit has both of the above circuits.Use these three circuits to simulate the user circuit under real conditions and evaluate the performance of the system.For the three kinds of circuits to be tested,100 times fault injection experiments were carried out under the traditional internal scrubbing system,the three module redundancy reinforcement scrubbing system and the configuration scrubbing system designed in this paper.Finally,the experiment shows that the internal scrubbing system designed in this paper has the best anti single upset performance.Experimental data shows that the fault tolerance rate of the internal scrubbing system proposed in this paper is 2.56 times that of the traditional internal scrubbing system.