Time Interleaved ADC Design For 56Gb/s SerDes Sysytem

In recent years,with the rapid development of information technology,the requirements for data processing capacity and information transmission rate are higher and higher.Serial communication is widely used in high-speed data transmission.Serializer-Deserializer（Ser Des）is an important part of high-speed serial link.At present,the high-speed Ser Des with a rate of 56Gb/s and above realizes the equalization of high-speed signals in DSP by using ADC+DSP architecture,so as to effectively deal with the problems of serious loss of channel high-frequency components and signal integrity.With the increasing signal rate,this ADC+DSP architecture has become the main implementation scheme of high-speed Ser Des.This paper studies the time interleaved ADC applied to high-speed Ser Des,in which the sub ADC adopts the successive approximation（SAR）ADC structure.The SAR ADC designed in this paper uses non loop structure to save the reset time of the comparator and improve the overall conversion speed.At the same time,the capacitor array adopts monotonic switching method to reduce the switching power consumption.Multiple comparators in the non loop structure adopt a two-stage architecture to enhance the anti-interference ability to the change of common mode voltage.In addition,the comparator adopts double tail structure and current bypass structure,which has the advantages of low offset voltage and low kickback noise.Based on the sub ADC,this paper designs a dual channel time interleaved ADC,which adopts the main sample and hold circuit and the high-speed sampling switch in the sub ADC structure to effectively suppress the timing mismatch between channels and realize high-quality input analog signal sampling.By fully overlapping the sub sampling switch and the main sampling and holding clock,the phase error tolerance of the clock signal is not less than 5%,so as to reduce the sampling error of the sub channel.This paper completes the circuit and layout design of time interleaved ADC based on CMOS 65nm process.The chip area including pad is 0.524mm² and the power consumption at power supply voltage is28.45m W.The simulation results show that when the total sampling rate of time interleaved ADC is 1GS/s and the input signal swing is 0.95V_pp,the effective bits are 6.38 bits and the spurious free dynamic range is49.08d B,which meets the design requirements.With the rapid growth of data transmission rate,the time interleaved ADC system designed in this paper has certain application value for high-speed Ser Des.