Research On The Realization Technology Of Convolutional Neural Network Mobile Net Chip Based On SoC FPGA

In recent years,Convolutional Neural Networks have been a popular solution for image classification and are widely used in the field of computer vision.However,due to the huge amount of parameters and calculations,the optimization of convolutional neural networks on the hardware platform is restricted,and the emergence of separable convolutions effectively solves this problem.In this thesis,based on the SoPC system,Mobile Net V2 is implemented fixed-point,and an acceleration scheme for target recognition in mobile scenarios with limited computing power is proposed.This thesis analyzes the special properties of the separable convolution of Mobile Net V2,compares a variety of hardware-based acceleration strategies for convolutional neural networks,and analyzes the feasibility and acceleration performance.Finally,drawing on Google’s TPU and MIT’s Eyeriss chip architecture,using the concept of systolic array,a new convolutional neural network inference architecture is designed in the SoPC system,and the parallel coefficient is determined by weighing network coefficients and hardware parameters.The thesis describes the hardware and software architecture and function distribution of the entire system.The system is divided into a software part and a hardware part.The hardware focuses on the realization of the calculation,and the software is mainly responsible for the transmission of data and the control of the process.The hardware part is completed in the PL part of the SoPC,which is mainly divided into four modules: control,calculation,storage and communication.The control module is mainly responsible for the process control of the hardware part.The computing module mainly includes the realization and optimization of computing layers such as convolution layer,BN layer,and activation function.Among them,the convolutional layer and BN layer are combined in the design,and the two perform pipelined pulsation calculations in a 3 × 3 × 16 PE array.For the two convolutions of DW and PW,the computing module accelerates in the same computing module by controlling the direction of the data flow.The storage module mainly uses the four-level storage resources on the board to realize the temporary storage of the feature map between layers,and uses the cache in the board to reduce the read and write time.The communication module mainly uses AXI-Data Mover to be responsible for the continuous data exchange between PL and PS.The software part mainly includes two parts: PS and PC.The PS part is responsible for accepting data,initializing and guiding the operation of the PL part.The PS part uses the NEON computing unit to accelerate the calculation steps such as the fully connected layer and Softmax,and finally it can form a pipeline with the calculation of the PL part,which reduces the operation time.The PC upper computer part is mainly responsible for the extraction,fixed point and packaged transmission of network parameters and processed images.This thesis establishes the Mobile Net-0.5-96 network acceleration system based on the SoPC system,and uses the ILSVRC-2012 dataset and life pictures for functional testing.The main frequency of the system is 150 MHz,the fixed-point strategy is INT16,and the processing time of each picture is 2.79 ms,which achieves 92% accuracy retention and achieves good performance.