Design Of Broadband RF Power Amplifier Based On 65nm CMOS Process

As the mainstream application band of wireless communication,frequency band below 8GHz has relatively good capacity and coverage,5G NR,Bluetooth,Wi Fi and other wireless communication standards are in this frequency band.In order to minimize the chip cost,broadband RF transceivers are required which applied in this band.As an important module of RF transceiver,power amplifier has a very important impact on the performance of transmitter.CMOS technology is widely used because of its low cost,high integration and compatibility with digital chips.Therefore,it is very valuable to research on the design of CMOS wideband power amplifier.This thesis focuses on the research and design of broadband power amplifiers in transceivers with coverage 75M～8GHz.Based on 65nm process,two broadband power amplifiers are designed to cooperatively cover this band.The first 75M～5GHz wideband power amplifier consists of power stage and driver stage,both stages adopt the self-bias stacked transistors structure,which reduce the possibility of transistor breakdown.Simultaneously,this power amplifier can force amplifier’s output impedance closed to 50Ω,which saves the extra matching network and reduces the chip area.The overall chip area is 520μm×416μm.The second 5～8GHz wideband power amplifier adopts differential structure,the drive stage and power stage are realized by cascode structure.The replacement of common gate transistor with thick gate transistor in power stage makes the amplifier can withstand higher supply voltage and improve the output power.Input matching network adopts lossy matching to expand bandwidth,output matching network is multi-node low Q matching network,and the overall chip area is 803μm×672μm.The post-simulation results show that the power gain of both PAs is greater than 18d B,S₁₁<-10d B,saturated output power is greater than 20d Bm,output 1d B compression point is greater than 18d Bm,and peak power added efficiency is greater than15%.The wideband power amplifier designed in this thesis meets the design specifications and can be used in transceiver systems below 8GHz.