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Design Of High-performance And Low-latency Montgomery Modular Multiplier For ECC

Posted on:2023-01-26Degree:MasterType:Thesis
Country:ChinaCandidate:H Q ZhangFull Text:PDF
GTID:2558307061463474Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Network servers based on elliptic curve cryptography(ECC)are faced with dilemma that authentication calculation of burst big data at cloud side.As the major part of ECC calculation amount and delay,modular multiplication is the key to restrict the design of high-performance and low-latency ECC computing system.A design of 256-bits high-performance and low-latency Montgomery modular multiplication is presented to relese the algorithm-dependent delay and reduce the critical path delay in traditional modular multiplication.A novel scheduling algorithm and its hardware architecture based on the non-least positive(NLP)representation is presented.A carry compensation scheme is designed on the basis of NLP,which splits the original 512-bits addition into a 256-bits addition and reduces the algorithm-dependent delay of the addition by 50%.Then,the data stream represented by NLP is scheduled by high-order Karatsuba-Ofman(KO),and the analytical model is established to explore the order of KO algorithm that makes NLP multipliers achieve compromise between critical path delay and area overhead.Meanwhile,a 16-bits NLP multiplication based on Booth coding is designed as the basic operation unit of the 256-bits large multiplier,which leads to the critical path delay and the algorithm-dependent delay of the original serial three-step 256-bits multiplication are reduced by 50%.Finally,a high-performance and low-latency ECC computing system is designed based on the proposed Montgomery modular multiplier.The function verification of module-level and system-level in the hardware design is completed at TSMC 28nm.The experimental results reveal that compared with ASSCC2019 and TCASII2021,the proposed ECC system and core unit of Montgomery modular multiplier are nearly 10 and 6.5times area-delay-product(AT)performance improvement,respectively.The frequency,calculation latency and area of the presented ECC system are 1GHz,80μs,and 0.355mm~2,respectively.The frequency,calculation latency and area of the proposed Montgomery modular multiplier are 1GHz,20ns,and 0.129mm~2,respectively.
Keywords/Search Tags:ECC, Montgomery modular multiplication circuit, NLP representation, KO algorithm
PDF Full Text Request
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