Research And Design Of Ka-Band Digital Attenuator Based On CMOS

In recent years,with the development of wireless communication technology,high performance phased-array transceivers are often used in the field of mil imeter wave communications system to improve the sensitivity.At the same time,the silicon-based semiconductor technology is continuously improved and the manufacturing cost is continuously reduced,which is gradually favored by the field of circuit design.Therefore,there is a broad research space for silicon-based millimeter wave digital attenuator used in phased array systems.A Ka-band 6-bit passive digital attenuator based on 40 nm CMOS process is designed in this dissertation firstly.The operating frequency of the passive digital attenuator is 27.5-31 GHz.On the basis of the traditional topology,the capacitor for phase compensation is adopted.According to the temperature and process corner characteristics of the chip,compensation measures are taken to reduce the error under different temperature and various process corner.The passive digital attenuator has been taped-out,and the test results are presented.The attenuation range is 31.5d B and the attenuation step is 0.5d B.The RMS attenuation error in the working frequency band is less than 0.5d B and the RMS additional phase shift error is less than2.8°.The insertion loss is less than 7.6d B and the chip size is 865μm × 520μm.In order to optimize the insertion loss of the passive digital attenuator,a Ka-band 6-bit active digital attenuator are designed based on 40 nm CMOS technology,with an operating frequency of 30-34 GHz.It combines the variable gain amplifier with the passive attenuator,which effectively improves the insertion loss of the circuit.The variable gain amplifier module adopts cross-coupling structure to achieve low phase shifting and the constant impedance;the passive attenuation module also employs the capacitor for phase compensation.The cosimulation results show that the active digital attenuator achieves an attenuation range of31.5d B and the attenuation step is 0.5d B.The RMS attenuation error in the working frequency band is less than 0.19 d B,and the RMS additional phase shift error is less than 1.48°.The gain of reference state is greater than 2.3d B,the static power consumption is 8.6m W,and the chip size is 642μm × 513μm.