Research And Design Of JESD204C Transmitting Circuits

With the development of the times,the industry has put forward higher requirements for data,especially in the data rate transmitted between analog-to-digital/digital-to-analog converters and logic devices.The JESD204C interface protocol supports the high-speed transmission of data between the converter and the system.It has the advantages of high performance and low power consumption,and meets the needs of the industry for high-speed interface circuits.Now more and more interface circuits choose to use the JESD204 interface protocol to provide better performance.This thesis studies the JESD204C transmission circuit,including a 64:1 multiplexer with a physical layer data rate of 25Gbps and circuit modules such as link layer scrambling,encoding and gearbox.Among them,the 64:1 multiplexer is composed of low-speed multiplexing and high-speed multiplexing modules.The high-speed module adopts a high-speed 4:1 parallel-serial conversion circuit,which is easier to achieve high speed than the tree-structured multiplexer.The low-speed module is based on a tree structure and uses a latch for retiming,which effectively avoids the occurrence of undesired phenomena in the multiplexing process and improves the quality of the output signal of the multiplexer.The link layer adopts parallel scrambling and parallel coding technology,which improves the working speed of the circuit.The gearbox adopts the technology of resource exchange performance,which improves the stability of the output signal.This thesis uses 65nm CMOS process to complete the layout design and post-simulation of the high-speed high-speed multiplexer.The chip area including the pad is 1.0×1.1mm~2,and the power consumption under 1.2V is 190m W.The simulation results show that the multiplexer can multiplex64 low-speed parallel signals to 1 high-speed serial signal of 25Gbps,and the jitter of the serial signal is less than 0.1UI.The designed link layer circuit conforms to the protocol standard and functions correctly.The research on the physical layer and data link layer of the JESD204C transmitter in this thesis has important application significance for the development of high-speed interface circuits and integrated circuits in related fields in China.