Design Of Transmitter For High-speed SerDes Interface Based On 28nm CMOS Process

In recent years,with the rapid development of electronic technology,the performance of consumer products put forward higher request,lead to electronic equipment for data transmission rate and bandwidth requirements are also rising.As the traditional parallel data transmission mode cannot meet the requirements of miniaturization of electronic products,Serializer(Ser Des)interface technology,one of the representatives of the emerging high-speed serial transmission technology,comes into being.However,with the continuous improvement of signal transmission rate,its signal processing rate can be up to tens or even hundreds of Gbps,at the same time will cause a series of signal integrity problems,such as channel attenuation of data signals,inter-symbol interference and crosstalk.Aiming at the above problems,this paper designs a Ser Des TX transmitter circuit with transmission rate up to 12.5Gb/s based on 28 nm CMOS TSMC technology for high-end Field Programmable Gate Array(FPGA)chip application.After 8B/10 B encoding,the data sent from the protocol layer to the physical layer is synchronized with the local clock,and the data can be adjusted to a width range of 16/20/32/40 bit.The low-speed parallel input data is serialized into high-speed serial data of 1bit through half-rate sampling,and then the high-frequency loss caused by signal transmission is compensated.Driven to the channel by the transmitter equalizer.TX FFE realizes the programmable pre-and post-weighted effect,and differential output swing using the proportional current mirror adjustable,compatible with a variety of high-speed serial protocols,to achieve a wide range of rate output.The main content of this paper is as follows:a)The classic structure of Ser Des transceiver and TX transmitter is introduced,and the basic principles and methods involved in the design process of high-speed serial link are described,including 8B/10 B coding technology,transmission line model,signal integrity analysis and the principle of de-emphasis compensation,so as to build a digital-analog hybrid design platform.b)Analyze the performance requirements of the sending end in the Ser Des transceiver,disassemble the key modules and introduce the advantages and disadvantages of each structure,select the structure required in this paper after comparative analysis,and then design the digital and analog modules by fully customized method.c)Design TX transmitter serializer,including clock frequency division module and parallel series module.According to the protocol,the serializer can realize the serialization of 16 bit,20bit,32 bit and 40 bit input,and the maximum working rate is6.25Gb/s.d)Design TX transmitter equalizer,which is mainly realized by delay module,tap coefficient control module and CML driver.The driver uses 3-tap FIR structure to realize programmable gain reduction of Pre-cursor 6d B and Post-cursor 12 d B.e)Complete layout design and post-imitation verification of single-channel Ser Des sender,and the overall layout area is 230μm × 350μm.The simulation results show that the transmission rate of the transmitter can be 0.5～12.5Gb/s,the output swing can be 0.259V～0.961 V,the maximum jitter is 0.088 UI,and the maximum power consumption is 34.5mW.